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| freescale semiconductor data sheet: advance information document number: mpc5674f rev. 9, 10/2012 ? freescale semiconductor, inc., 2008-2012. all rights reserved. mpc5674f tepbga?516 27mm x 27mm tepbga?324 23mm x 23mm tepbga?416 27mm x 27mm ? dual issue, 32-bit cpu core complex (e200z7) ? compliant with the power architecture ? embedded category ? 16 kb i-cache and 16 kb d-cache ? includes an instruction set enhancement allowing variable length encoding (vle), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction ? includes signal processing extension (spe2) instruction support for digital signal processing (dsp) and single-precision floating point operations ? 4 mb on-chip flash ? supports read during program and erase operations, and multiple blocks allowing eeprom emulation ? 256 kb on-chip general-purpose sram including 32 kb of standby ram ? two direct memory access controller (edma2) blocks ? one supporting 64 channels ? one supporting 32 channels ? interrupt controller (intc) ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or ram from multiple bus masters ? external bus interface (ebi) fo r calibration and application development (not availa ble on all packages) ? system integration unit (siu) ? error correction status module (ecsm) ? boot assist module (bam) supports serial bootload via can or sci ? two second-generation enha nced time processor units (etpu2) that share code and data ram. ? 32 standard channels per etpu2 ? 24 kb code ram ? 6 kb parameter (data) ram ? enhanced modular input output system supporting 32 unified channels (e mios) with each channel capable of single action, double action, pulse width modulation (pwm) and modulus counter operation ? four enhanced queued anal og-to-digital converters (eqadc) ? support for 64 analog channels ? includes one absolute reference adc channel ? includes eight decimation filters ? four deserial serial periph eral interface (dspi) modules ? three enhanced serial communication interface (esci) modules ? four controller area network (flexcan) modules ? dual-channel flexray controller ? nexus development inte rface (ndi) per ieee-isto 5001-2003/5001-2008 standard ? device and board test support per joint test action group (jtag) (ieee 1149.1) ? on-chip voltage regulator controller regulates supply voltage down to 1.2 v for core logic mpc5674f microcontroller data sheet covers: mpc5674f and mpc5673f
mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 2 table of contents 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 orderable parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 mpc567xf family differences . . . . . . . . . . . . . . . . . . . .4 2 mpc5674f blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 324-ball tepbga pin assignments . . . . . . . . . . . . . . . .6 3.2 416-ball tepbga pin assignments . . . . . . . . . . . . . . . .9 3.3 516-ball tepbga pin assignments . . . . . . . . . . . . . . .14 3.4 signal properties and muxing . . . . . . . . . . . . . . . . . . . .19 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 4.2.1 general notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . .23 4.3 emi (electromagnetic interference) characteristics . . .24 4.4 esd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.5 pmc/por/lvi electrical specific ations . . . . . . . . . . . .25 4.6 power up/down sequencing . . . . . . . . . . . . . . . . . . . .29 4.6.1 power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.6.2 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.6.3 power sequencing and por dependent on v dda 30 4.7 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .30 4.7.1 i/o pad current specifications . . . . . . . . . . . . .33 4.7.2 lvds pad specifications . . . . . . . . . . . . . . . . . .35 4.8 oscillator and fmpll electrical characteristics . . . . . 35 4.9 eqadc electrical characteristics . . . . . . . . . . . . . . . . 37 4.9.1 adc internal resource measurements . . . . . . 39 4.10 c90 flash memory electrical characteristics . . . . . . . 40 4.11 ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.11.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.11.2 pad ac specifications . . . . . . . . . . . . . . . . . . . 44 4.12 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.12.1 generic timing diagrams. . . . . . . . . . . . . . . . . 45 4.12.2 reset and configuration pin timing. . . . . . . . . 46 4.12.3 ieee 1149.1 interface timing. . . . . . . . . . . . . . 47 4.12.4 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.12.5 external bus interface (ebi) timing . . . . . . . . . 53 4.12.6 external interrupt timing (irq pin) . . . . . . . . . 57 4.12.7 etpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.12.8 emios timing . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.12.9 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.1 324-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 516-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 appendix asignal properties and muxing . . . . . . . . . . . . . . . . . . 73 appendix brevision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 ordering information mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 3 1 ordering information 1.1 orderable parts figure 1 and table 1 describe and list the orderable part numbers for the mpc5674f. figure 1. mpc5674f orderable part number description table 1. orderable part numbers freescale part number package description speed (mhz) 1 1 for the operating mode frequency of various blocks on the device, see ta b l e 2 7 . operating temperature 2 2 the lowest ambient operating te mperature is referenced by t l ; the highest ambient operating te mperature is referenced by t h . nominal max 3 (f max ) 3 speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 270 mhz parts allow for 264 mhz system clock + 2% fm. min (t l )max (t h ) spc5673ff3mvr3 416 pbga, no ebi, pb-free 264 270 ?40 c 125 c spc5673ff3mvy3 516 pbga, w/ebi, pb-free 264 270 ?40 c 125 c spc5673ff3mvv2 516 pbga, w/ebi, snpb 264 270 ?40 c 125 c spc5674ff3mvr3 416 pbga, no ebi, pb-free 264 270 ?40 c 125 c spc5673ff3mvy2 516 pbga, w/ebi, pb-free 200 200 ?40 c 125 c spc5674ff3mvy3 516 pbga, w/ebi, pb-free 264 270 ?40 c 125 c SPC5674FF3MVV3 516 pbga, w/ebi, snpb 264 270 ?40 c 125 c spc5674ff3mvz2 324 pbga, no ebi, pb-free 200 200 ?40 c 125 c mpc m r qualification status core code device number fab revision id revision of silicon temperature range package identifier operating frequency (mhz) tape and reel status temperature range m = ?40 c to 125 c package identifier vz = 324 bga pb-free vr = 416 bga pb-free vy = 516 bga pb-free vv = 516 bga snpb operating frequency 2=200mhz 3=264mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre qualification m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow note: not all options are available on all devices. refer to ta b l e 1 . 5674f vr revision of silicon 3 = rev 3 f 3 3 fab revision id f=atmc mpc5674f microcontroller data sheet, rev. 9 ordering information freescale semiconductor 4 1.2 mpc567xf family differences table 2 lists the differences between the mpc567xf devices. refer to the mpc5674f reference manual for a full feature list and comparison. table 2. mpc567xf family differences feature mpc5674f mpc5674f mpc5673f mpc5673f package 416 bga 516 bga 324 bga 416 bga 516 bga 324 bga flash 4 mb 4 mb 3 mb 3 mb sram 256 kb 256 kb 192 kb 192 kb external bus yes (516 bga only) no yes (516 bga only) no serial 3 2 3 2 esci_a yes yes yes yes esci_b yes yes yes yes esci_c yes no yes no spi 4 3 4 3 dspi_a yes no yes no dspi_b yes yes yes yes dspi_c yes yes yes yes dspi_d yes yes yes yes emios 32 channel 22 channel 32 channel 22 channel etpu2 64 channel 47 channel 64 channel 47 channel etpu_a yes (32 ch) yes (26 ch) yes yes (26 ch) etpu_b yes (32 ch) yes (21 ch, no tcrclk) yes yes (21 ch, no tcrclk) adc 64 channel 48 channel 64 channel 48 channel eqadc_a yes (64 ch) 1 1 there are are two pairs of 24 channels plus 16 shar ed channels. this gives 64 channels total: 40 per adc (since 16 are shared). yes (24 ch) yes (64 ch) 1 yes (24 ch) eqadc_b yes (24 ch) yes (24 ch) mpc5674f blocks mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 5 2 mpc5674f blocks 2.1 block diagram figure 2 shows a top-level block diagram of the mpc5674f device. figure 2. block diagram 3 pin assignments the figures in this section show the primary pin functi on. for the full signal proper ties and muxing table, see appendix a, signal properties and muxing . jtag mpc5674f flexcan flexcan flexcan flexcan esci dspi dspi dspi dspi esci etpu2 32 6kb data 24kb code emios 32 channel channel etpu2 32 channel ram ram crossbar switch mpu edma2 edma2 64 channel 32 channel interrupt controller spe2 vle mmu power? 16k i-cache 16k d-cache e200z7 core nexus flexray ebi (calibration & development use) adci amux adci adc i/o bridge 4mb flash 256kb sram (32k s/b) boot assist module siu i/o bridge adc ? analog to digital convertor adci ? adc interface amux ? analog multiplexer decfil ? decimation filter dspi ? deserial/serial peripheral interface ebi ? external bus interface ecsm ? error correction status module edma2 ? enhanced direct memory access emios ? enhanced modular i/o system eqadc ? enhanced queued a/d converter module esci ? enhanced serial communications interface etpu2 ? enhanced time processing unit 2 flexcan ? controller area network mmu ? memory management unit mpu ? memory protection unit s/b ? stand-by siu ? system integration unit spe2 ? signal processing engine 2 sram ? general-purpose static ram vle ? variable length instruction encoding legend esci adc adc adc eqadc eqadc decfilx8 ecsm mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 6 3.1 324-ball tepbga pin assignments figure 3 shows the 324-ball tepbga pin assignments. the same information is shown in figure 4 through figure 5 . figure 3. mpc5674f 324-ball tepbga (full diagram) vss 1234567891011121314 vdd rstout ana0 ana15 vdda_a0 a vddeh1 vss vdd test ana2 ana3 ana7 vssa_a1 b vss vdd ana8 ana10 ana13 ana17 ana19 ana21 ana23 anb10 anb9 c vss vdd ana11 ana14 ana18 ana20 anb8 anb13 d e f g vss vss vss vss vss vss vss vss vss vss vss vss h vss vdde2 vss vss j k l m vss vdd emios18 w vss emios14 y vdd emios13 aa vss vdd emios11 ab ana12 ana9 ana1 vrl_a vdde2 fr_a_ ana5 ana4 etpua21 ana16 engclk ana6 ana22 emios9 emios8 vdd vddeh4 pcsb2 boot- rdy pllcfg0 reset jcomp tms mdo13 tdo tdi tck fr_a_ emios5 emios2 sckb scka pcsb0 fr_a_ pcsa5 emios10 emios3 sinb sina emios0 fr_b_ pcsa0 emios7 emios4 soutb souta emios1 15 16 17 18 19 20 21 22 vrl_b anb3 anb6 anb7 anb22 vss anb4 anb5 anb19 anb23 vss anb11 anb12 anb14 anb16 anb20 vss anb17 anb18 vss vss vss vss vss vss vss vss vss cnrxb vss cntxb cnrxd vss vdd vddsyn cnrxa sckc sinc vss soutc pcsc0 vss a b c d e f g h j k l m anb2 vrh_b anb1 anb15 xtal cntxd anb21 etpuc12 etpub10 etpub11 etpub9 vdd vdd33_3 cnrxc cntxc emios31 emios30 emios26 emios23 emios29 emios28 emios25 cntxa emios24 emios20 vddeh4 vdd 12345678910111213141516171819202122 mseo1 evti n mdo1 p r t u v mcko mdo0 vdde2 evto mdo5 mdo4 mdo3 mdo2 vdde2 mdo8 mdo7 mdo6 mdo15 mdo11 mdo10 mdo9 vdd33_2 mdo14 vdde2 mdo12 etpub0 vddeh6 etpub8 etpub6 tcrclkb etpub16 etpub5 etpub4 etpub1 etpub17 etpub3 etpub2 etpub19 etpub18 vddeh6 regctl etpub31 etpub30 vsssyn vdd n p r t u v vddreg regsel vssfl extal vss vdde2 vdde2 vss vss vdde2 vdde2 vss vss vss vss vss w y aa ab etpua23 etpua20 etpua13 etpua10 etpua5 etpua1 tcrclka etpua25 etpua22 etpua14 etpua11 etpua6 etpua2 etpua26 etpua31 etpua24 etpua15 etpua12 etpua9 etpua3 vdd etpua30 etpua27 etpua17 etpua16 etpua4 vstby emios22 emios15 emios17 emios12 emios27 emios19 emios21 emios16 tx_en tx_en rx tx etpuc20 etpuc27 etpuc31 etpub7 etpuc14 etpuc18 etpuc23 etpuc30 etpub13 etpuc13 etpuc19 etpuc22 etpuc26 etpuc29 etpub14 etpuc9 etpuc17 etpuc21 etpuc24 etpuc25 etpuc28 etpuc10 etpuc11 etpuc4 etpuc2 tcrclkc etpuc3 etpuc0 pllcfg1 vdda_ b0 ref? bypcb1 ref? bypcb vdda_ b1 vssa_ b0 pllcfg2 vddeh1 mseo0 vdd fr_b_ tx vss fr_b_ rx etpub12 vddeh7 mpc5674f 324 tepbga (as viewed from top through the package) vrh_a ref? bypcb1 anb0 ref? bypca vdda_a0 vddeh7 etpuc1 etpuc5 vddeh7 etpua0 cfg1 vdde2 pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 7 figure 4. mpc5674f 324-ball tepbga (1 of 2) vss 1234567891011 vdd rstout ana0 ana15 vdda_a0 a vddeh1 vss vdd test ana2 ana3 ana7 vssa_a1 b vss vdd ana8 ana10 ana13 ana17 ana19 ana21 c vss vdd ana11 ana14 ana18 ana20 d e f g vss vss vss vss vss vss vss vss vss h vdde2 vss vss j k l m vss vdd w vss y vdd aa vss vdd ab ana12 ana9 ana1 vrl_a vdde2 fr_a_ ana5 ana4 etpua21 ana16 engclk ana6 emios9 emios8 vdd vddeh4 pcsb2 boot- rdy pllcfg0 reset jcomp tms mdo13 tdo tdi tck fr_a_ emios5 emios2 sckb scka pcsb0 fr_a_ pcsa5 emios10 emios3 sinb sina emios0 fr_b_ pcsa0 emios7 emios4 soutb souta emios1 a b c d j k l m mseo1 evti n mdo1 p r t u v mcko mdo0 vdde2 evto mdo5 mdo4 mdo3 mdo2 vdde2 mdo8 mdo7 mdo6 mdo15 mdo11 mdo10 mdo9 vdd33_2 mdo14 vdde2 mdo12 n p vdde2 vdde2 vss vdde2 vdde2 vss w y aa ab etpua23 etpua20 etpua13 etpua10 etpua5 etpua1 tcrclka etpua25 etpua22 etpua14 etpua11 etpua6 etpua2 etpua26 etpua31 etpua24 etpua15 etpua12 etpua9 etpua3 vdd etpua30 etpua27 etpua17 etpua16 etpua4 vstby tx_en tx_en rx tx pllcfg1 pllcfg2 vddeh1 mseo0 vdd fr_b_ tx vss fr_b_ rx mpc5674f 324 tepbga (as viewed from top through the package) vrh_a ref? bypca vdda_a0 etpua0 cfg1 vdde2 1234567891011 mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 8 figure 5. mpc5674f 324-ball tepbga (2 of 2) 12 13 14 a b ana23 anb10 anb9 c anb8 anb13 d vss vss vss vss j k l m emios18 w emios14 y emios13 aa emios11 ab ana22 15 16 17 18 19 20 21 22 vrl_b anb3 anb6 anb7 anb22 vss anb4 anb5 anb19 anb23 vss anb11 anb12 anb14 anb16 anb20 vss anb17 anb18 vss vss vss vss vss vss vss vss vss cnrxb vss cntxb cnrxd vss vdd vddsyn cnrxa sckc sinc vss soutc pcsc0 vss a b c d e f g h j k l m anb2 vrh_b anb1 anb15 xtal cntxd anb21 etpuc12 etpub10 etpub11 etpub9 vdd vdd33_3 cnrxc cntxc emios31 emios30 emios26 emios23 emios29 emios28 emios25 cntxa emios24 emios20 vddeh4 vdd n p etpub0 vddeh6 etpub8 etpub6 tcrclkb etpub16 etpub5 etpub4 etpub1 etpub17 etpub3 etpub2 etpub19 etpub18 vddeh6 regctl etpub31 etpub30 vsssyn vdd n p r t u v vddreg regsel vssfl extal vss vss vss vss vss vss w y aa ab emios22 emios15 emios17 emios12 emios27 emios19 emios21 emios16 etpuc20 etpuc27 etpuc31 etpub7 etpuc14 etpuc18 etpuc23 etpuc30 etpub13 etpuc13 etpuc19 etpuc22 etpuc26 etpuc29 etpub14 etpuc9 etpuc17 etpuc21 etpuc24 etpuc25 etpuc28 etpuc10 etpuc11 etpuc4 etpuc2 tcrclkc etpuc3 etpuc0 vdda_ b0 ref? bypcb1 ref? bypcb vdda_ b1 vssa_ b0 etpub12 vddeh7 mpc5674f 324 tepbga (as viewed from top through the package) ref? bypcb1 anb0 vddeh7 etpuc1 etpuc5 vddeh7 12 13 14 15 16 17 18 19 20 21 22 pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 9 3.2 416-ball tepbga pin assignments figure 6 shows the 416-ball tepbga pin assignments in one figure. the same information is shown in figure 7 through figure 10 . figure 6. mpc5674f 416-ball tepbga (full diagram) vssfl regctl etpub26 tdo mdo15 vdde2 vdde2 vdde2 vss 12345678910111213141516 vdd rstout ana0 ana15 vdda_a0 vrh_a an28 an32 an36 vdda_b0 a vddeh1 vss vdd test ana1 ana5 ana14 vdda_a1 ref? an24 an27 an29 an33 vdda_b1 b vss vdd ana2 ana6 ana13 ana17 ana19 ana21 ana23 an26 an30 an34 an37 c vss vdd ana3 ana12 ana18 ana20 an25 an31 an35 an39 d e f g vss vss vss vss vss vss vss vss vss vss vss vss h vss vdde2 vss vss j k l m vss vdde2 vdd ac vss fr_a_ emios5 ad vss fr_a_ emios6 ae vss vdde2 emios7 af ana7 ana9 ana4 mpc5674f 416-ball tepbga (as viewed from top through the package) vrl_a vssa_a1 pcsa1 fr_a_ ana11 ana8 etpua30 ana16 vdd pcsa5 ana10 ana22 vddeh4 vddeh3 pcsb1 pcsb4 pcsa2 etpua2 vstby rxda txda vdd33_1 vdd tdi vdde2 vdd engclk fr_b_ emios2 pcsb3 scka souta pcsb0 fr_b_ pcsa0 pcsa4 emios3 emios0 sckb pcsa3 sinb fr_b_ pcsb5 vddeh3 emios4 emios1 pcsb2 sina soutb 17 18 19 20 21 22 23 24 25 26 vrl_b vrh_b anb14 anb17 anb21 anb23 vss ref? anb6 anb10 anb15 anb18 anb22 vss anb0 anb4 anb5 anb12 anb16 anb19 vss anb2 anb9 anb13 vss vddeh7 vddeh7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss pcsc1 vss rxdc pcsc3 vss vdd vddsyn sinc pcsc2 pcsc5 vss vddeh4 txdc vss a b c d e f g h j k l m anb1 an38 anb11 anb7 anb8 anb3 xtal vddeh5 vssa_b0 anb20 etpuc7 etpub15 etpub14 vddeh7 vdd vddeh6 vddeh5 cnrxd cnrxb sckc cntxd cntxb pcsc0 cnrxc cnrxa soutc cntxc cntxa pcsc4 vdd 1234567891011121314151617181920212223242526 wkpcfg vdd n vddeh1 p r t u v w y aa ab pllcfg2 rdy rxdb txdb pllcfg0 evti reset jcomp mseo1 mcko vdde2 mdo1 mdo0 mseo0 evto mdo5 mdo4 mdo3 mdo2 vdde2 mdo8 mdo7 mdo6 mdo11 mdo10 mdo9 vdd33_2 mdo14 mdo13 mdo12 vdd tms tck vddeh6 etpub11 etpub12 etpub13 etpub7 etpub8 etpub9 etpub10 etpub3 etpub4 etpub5 etpub0 etpub1 etpub2 etpub19 etpub20 regsel etpub25 etpub24 etpub23 etpub29 etpub28 etpub27 vdd33_3 etpub30 vsssyn vdd n p r t u v w y aa ab etpub18 etpub17 etpub16 etpub21 etpub22 tcrclkb vddreg etpub31 extal vss vdde2 vss vss vdde2 vss vss vdde2 vss vdde2 vdde2 vdde2 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss ac ad ae af etpua27 etpua23 etpua19 etpua15 etpua11 etpua7 etpua3 tcrclka etpua28 etpua24 etpua20 etpua16 etpua12 etpua8 etpua4 etpua31 etpua29 etpua25 etpua21 etpua17 etpua14 etpua9 etpua5 etpua1 etpua26 etpua22 etpua18 etpua13 etpua10 etpua6 emios8 emios9 emios10 emios11 emios14 emios15 emios13 emios12 emios18 emios19 emios17 emios16 emios22 emios23 emios21 emios20 emios27 emios26 emios25 emios24 emios31 emios30 emios29 emios28 rx tx_en tx_en rx tx tx bypca bypcb etpuc11 etpuc15 etpuc19 etpuc23 etpuc27 etpuc31 etpuc8 etpuc12 etpuc16 etpuc20 etpuc24 etpuc28 etpuc9 etpuc13 etpuc17 etpuc21 etpuc25 etpuc29 etpuc10 etpuc14 etpuc18 etpuc22 etpuc26 etpuc30 etpuc4 etpuc5 etpuc6 etpuc3 etpuc1 tcrclkc etpuc2 etpuc0 etpub6 etpua0 vdde2 boot? cfg1 pllcfg1 ref? bypca1 ref? bypcb1 mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 10 figure 7. mpc5674f 416-ball tepbga (1 of 4) 12345678910111213 12345678910111213 vdd vss txda bootcfg1 etpua28 etpua24 etpua20 etpua16 etpua12 etpua8 etpua4 etpua0 vss rstout ana0 ana15 vdda_a0 vrh_a an28 vddeh1 vdd test ana1 ana5 ana14 vdda_a1 refbypca an24 an27 vss vdd ana2 ana6 ana13 ana17 ana19 ana21 ana23 an26 vss vdd ana3 ana12 ana18 ana20 an25 vss vss vss vss vss vss vss vss vss vss vss vss vss vdde2 vss vss ana7 ana9 ana4 vrl_a vssa_a1 ana11 ana8 etpua30 ana16 ana10 ana22 etpua2 vstby rxda vdd33_1 wkpcfg vdd rxdb etpua27 etpua23 etpua19 etpua15 etpua11 etpua7 etpua3 tcrclka etpua31 etpua29 etpua25 etpua21 etpua17 etpua14 etpua9 etpua5 etpua1 etpua26 etpua22 etpua18 etpua13 etpua10 etpua6 a b e f g h j k l m n c d a b e f g h j k l m n c d mpc5674f 416-ball tepbga (as viewed from top through the package) (1 of 4) refbyp- ca1 pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 11 figure 8. mpc5674f 416-ball tepbga (2 of 4) 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 an32 an36 vdda_b0 an29 an33 vdda_b1 an30 an34 an37 an31 an35 an39 vrl_b vrh_b anb14 anb17 anb21 anb23 vss refbypcb anb6 anb10 anb15 anb18 anb22 vss anb0 anb4 anb5 anb12 anb16 anb19 vss anb2 anb9 anb13 vss vddeh7 vddeh7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss anb1 an38 anb11 anb7 anb8 anb3 vssa_b0 anb20 etpuc7 etpub15 etpub14 vddeh7 vddeh6 etpub11 etpub12 etpub13 etpuc11 etpuc15 etpuc19 etpuc23 etpuc27 etpuc31 etpuc8 etpuc12 etpuc16 etpuc20 etpuc24 etpuc28 etpuc9 etpuc13 etpuc17 etpuc21 etpuc25 etpuc29 etpuc10 etpuc14 etpuc18 etpuc22 etpuc26 etpuc30 etpuc4 etpuc5 etpuc6 etpuc3 etpuc1 tcrclkc etpuc2 etpuc0 a b e f g h j k l m n c d a b e f g h j k l m n c d mpc5674f 416-ball tepbga (as viewed from top through the package) (2 of 4) refbyp- cb1 mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 12 figure 9. mpc5674f 416-ball tepbga (3 of 4) vdde2 vdde2 tdo mdo15 p r v w y aa ab ac ad ae af t u p r v w y aa ab ac ad ae af t u vss vdde2 tdi vdd pllcfg1 reset mcko mseo0 mdo3 mdo7 mdo10 mdo13 tck vss vdde2 vdd vss emios5 emios6 vss emios7 pcsa1 vdd pcsa5 vddeh4 vddeh3 pcsb1 pcsb4 pcsa2 vdd vdde2 engclk fr_b_tx emios2 pcsb3 scka souta pcsb0 fr_b_rx pcsa0 pcsa4 emios3 emios0 sckb pcsa3 sinb pcsb5 vddeh3 emios4 emios1 pcsb2 sina soutb vddeh1 pllcfg2 rdy txdb pllcfg0 evti jcomp mseo1 vdde2 mdo1 mdo0 evto mdo5 mdo4 mdo2 vdde2 mdo8 mdo6 mdo11 mdo9 vdd33_2 mdo14 mdo12 vdd tms vss vdde2 vss vss vdde2 vss vss vdde2 vss vdde2 vdde2 vdde2 emios8 emios9 emios10 emios11 12345678910111213 12345678910111213 mpc5674f 416-ball tepbga (as viewed from top through the package) (3 of 4) vdde2 vdde2 fr_b_ tx_en fr_a_tx fr_a_rx fr_a_ tx_en pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 13 figure 10. mpc5674f 416-ball tepbga (4 of 4) regctl etpub26 p r v w y aa ab ac ad ae af t u 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 pcsc1 vss rxdc pcsc3 vss vdd vddsyn sinc pcsc2 pcsc5 vss vddeh4 txdc vss xtal vddeh5 vdd vddeh6 vddeh5 cnrxd cnrxb sckc cntxd cntxb pcsc0 cnrxc cnrxa soutc cntxc cntxa pcsc4 vdd etpub7 etpub8 etpub9 etpub10 etpub3 etpub4 etpub5 etpub0 etpub1 etpub2 etpub19 etpub20 regsel etpub25 etpub24 etpub23 etpub29 etpub28 etpub27 vdd33_3 etpub30 vsssyn vdd etpub18 etpub17 etpub16 etpub21 etpub22 tcrclkb etpub31 extal vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss emios14 emios15 emios13 emios12 emios18 emios19 emios17 emios16 emios22 emios23 emios21 emios20 emios27 emios26 emios25 emios24 emios31 emios30 emios29 emios28 etpub6 p r v w y aa ab ac ad ae af t u mpc5674f 416-ball tepbga (as viewed from top through the package) (4 of 4) vddreg vssfl mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 14 3.3 516-ball tepbga pin assignments figure 11 shows the 516-ball tepbga pin assignments in one figure. the same information is shown split into four quadrants in figure 12 through figure 15 . figure 11. mpc5674f 516-ball tepbga (full diagram) tcrclkc vss vss mpc5674f 516-ball tepbga 12345678910111213141516 vdd rstout ana0 ana15 vdda_a0 vrh_a an28 an29 an36 vdda_b0 a vddeh1 vss vdd test ana1 ana5 ana14 vdda_a1 ref? an24 an27 an30 an32 vdda_b1 b vss vdd ana2 ana6 ana13 ana17 ana19 ana21 ana22 an25 an31 an34 an39 c vss vdd ana3 ana12 ana18 ana20 an26 an33 an35 an38 d e f g vss vss vss vss vss vss vss vss vss vss vss vss h vss vdde2 vss vss j k l m vss vdde2 vdd ac vss fr_a_ ad vss fr_a_ ae vdde2 d_ af ana8 ana7 ana4 (as viewed from top through the package) vrl_a vssa_a1 pcsa1 fr_a_ ana11 ana9 etpua30 ana16 vdd pcsa0 ana10 ana23 vddeh4 vddeh3 tcrclka vstby vdd33_1 vdd tms vdde2 vdd engclk fr_b_ sinb soutb d_cs0 fr_b_ pcsb5 pcsa4 pcsb1 scka fr_b_ pcsa2 vddeh3 pcsb0 pcsb4 d_ta 17 18 19 20 21 22 23 24 25 26 vrl_b vrh_b anb12 anb18 anb21 anb23 ref? anb4 anb10 anb13 anb19 anb22 vss anb0 anb7 anb6 anb11 anb15 anb20 vss anb2 anb14 anb16 vss vddeh7 vddeh7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss pcsc1 vss rxdc pcsc3 vss vdd vddsyn sinc pcsc2 pcsc5 vss vddeh4 txdc a b c d e f g h j k l m anb1 an37 anb9 anb5 anb8 anb3 xtal vddeh5 vssa_b0 anb17 etpuc7 vddeh7 vdd vddeh6 vddeh5 cnrxd cntxb sckc cntxd cnrxa pcsc0 cnrxc cntxa soutc cntxc cnrxb pcsc4 vdd 1234567891011121314151617181920212223242526 vdd n vddeh1 p r t u v w y aa ab wkpcfg pllcfg1 mseo1 rxdb pllcfg2 reset jcomp rdy mseo0 vdde2 mcko mdo2 mdo0 evto evti mdo10 mdo9 mdo7 vdd33_1 mdo15 mdo14 mdo13 vdd tdo tck vddeh6 etpub12 etpub14 etpub8 etpub10 etpub2 etpub0 vddreg etpub26 etpub27 etpub24 vdd33_3 etpub28 vsssyn vdd n p r t u v w y aa ab etpub4 etpub5 etpub6 etpub16 regctl etpub7 etpub30 vssfl extal vss vdde2 vss vss vdde2 vss vss vdde2 vss vdde2 vdde2 vdde2 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss ac ad ae af etpua27 etpua23 etpua19 etpua11 etpua5 etpua1 etpua28 etpua24 etpua20 etpua13 etpua7 etpua2 etpua31 etpua29 etpua25 etpua21 etpua15 etpua8 etpua9 etpua22 etpua17 etpua3 etpua4 emios0 emios2 emios3 emios4 emios7 emios6 emios5 emios13 emios12 emios10 emios9 emios23 emios16 emios15 emios20 emios31 emios18 emios21 emios14 emios28 emios27 emios26 emios25 rx tx_en tx_en rx tx tx bypca bypcb etpuc12 etpuc17 etpuc23 etpuc29 etpuc8 etpuc13 etpuc18 etpuc24 etpuc30 etpuc9 etpuc14 etpuc20 etpuc26 etpuc31 etpuc10 etpuc15 etpuc21 etpuc27 etpuc4 etpuc5 etpuc6 etpuc3 etpuc1 etpuc2 etpuc0 tcrclkb vdde8 vdd33_1 d_add16 d_add17 d_cs3 d_cs2 vss vdde8 vdde9 vss vdde8 vdde10 d_dat9 vdde10 d_dat6 vdde10 d_oe d_ale d_rd_ vss vdde10 vdde9 vss vdd33_6 d_dat15 d_dat14 vss vss vss vss vss vss vss vss vss vdde8 vss vss vss vdde8 vdde8 vss vss vdde10 vss vdde10 d_add29 vdd33_4 d_ts d_cs1 d_add21 vdde9 vdde9 vdde9 vdde9 vdd33_4 vdde9 vdde10 etpua26 vss vss vdd vss vss wr d_bdip etpua18 etpuc11 d_we0 etpua14 etpua16 etpuc16 etpuc19 etpua12 etpuc22 txdb rxda txda etpua6 etpua10 etpuc28 etpuc25 boot? cfg1 boot? cfg0 etpua0 d_dat13 d_dat12 d_dat11 d_dat10 vdde2 vdde2 vdde2 vdde2 pllcfg0 d_dat8 d_dat7 d_dat5 d_we2 d_we3 d_dat2 d_dat3 d_dat4 d_add9 d_add10 d_add11 d_we1 etpub13 d_dat0 d_dat1 d_add15 d_add14 d_add13 d_add12 etpub9 etpub15 d_add20 d_add19 d_add18 etpub3 etpub17 etpub11 etpub23 etpub1 mdo3 etpub22 etpub21 mdo11 mdo12 etpub31 pcsa5 emios1 emios11 emios17 emios19 emios29 tdi souta sckb pcsb3 emios8 emios22 emios24 pcsa3 pcsb2 d_add22 d_add25 d_add28 sina d_add26 d_add23 d_add30 d_add24 d_add27 clkout emios30 etpub20 etpub19 etpub18 regsel etpub29 etpub25 vdde2 mdo6 mdo5 mdo4 mdo8 mdo1 ref? bypca1 ref? bypcb1 pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 15 figure 12. mpc5674f 516-ball tepbga (1 of 4) mpc5674f 516-ball tepbga (as viewed from top through the package) (1 of 4) vdd rstout ana0 ana15 vdda_a0 vrh_a an28 vddeh1 vss vdd test ana1 ana5 ana14 vdda_a1 an24 an27 vss vdd ana2 ana6 ana13 ana17 ana19 ana21 ana22 an25 vss vdd ana3 ana12 ana18 ana20 an26 vss vss vss vss vss vss vss vss vss vss vss vss vss vdde2 vss vss ana8 ana7 ana4 vrl_a vssa_a1 ana11 ana9 etpua30 ana16 ana10 ana23 pllcfg1 rxdb pllcfg2 etpua27 etpua23 etpua19 etpua11 etpua5 etpua1 etpua28 etpua24 etpua20 etpua13 etpua7 etpua2 etpua31 etpua29 etpua25 etpua21 etpua15 etpua8 etpua9 etpua22 etpua17 etpua3 etpua4 vdde8 vss vss vss vss vss vss vdde8 vss vss vdde8 vdde8 etpua26 vss vss vdd etpua18 etpua14 etpua16 etpua12 rxda txda etpua6 etpua0 12345678910111213 a b e f g h j k l m n c d a b e f g h j k l m n c d 12345678910111213 refbypca bootcfg0 txdb tcrclka etpua10 bootcfg1 vdd reset vdde8 d_we0 d_we2 d_we3 vstby vdd33_1 wkpcfg d_bdip pllcfg0 ref- bypca1 mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 16 figure 13. mpc5674f 516-ball tepbga (2 of 4) anb23 vss vss mpc5674f 516- ball tepbga (as viewed from top through the package) (2 of 4) an30 an32 vdda_b1 an31 an34 an39 an33 an35 an38 anb4 anb10 anb13 anb19 anb22 vss anb0 anb7 anb6 anb11 anb15 anb20 vss anb2 anb14 anb16 vss vddeh7 vddeh7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss anb1 an37 anb8 anb3 vssa_b0 anb17 etpuc7 vddeh7 vddeh6 etpuc12 etpuc17 etpuc23 etpuc29 etpuc8 etpuc13 etpuc18 etpuc24 etpuc30 etpuc9 etpuc14 etpuc20 etpuc26 etpuc31 etpuc10 etpuc15 etpuc21 etpuc27 etpuc4 etpuc5 etpuc6 etpuc3 etpuc1 etpuc2 etpuc0 vdde10 d_dat9 vdde10 d_dat6 vdd33_6 d_dat15 d_dat14 vss vss vss vss vss vss vdde10 vss vdde10 vdde10 vss vss tcrclkc etpuc11 etpuc16 etpuc19 etpuc22 etpuc28 etpuc25 d_dat13 d_dat12 d_dat11 d_dat10 d_dat8 d_dat7 d_dat5 d_dat2 d_dat3 d_dat4 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 a b e f g h j k l m n c d a b e f g h j k l m n c d refbypcb an29 an36 vdda_b0 vrl_b vrh_b anb12 anb18 anb21 anb9 anb5 ref- bypcb1 pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 17 figure 14. mpc5674f 516-ball tepbga (3 of 4) mpc5674f 516-ball tepbga (as viewed from top through the package) (3 of 4) vss fr_a_rx vdd fr_b_rx pcsb5 pcsa4 pcsb1 emios3 d_ts sina d_add26 d_add23 d_add30 vss vdde2 vdd vss fr_a_tx vdde2 pcsa1 fr_a_ pcsa0 vddeh4 vddeh3 vdd vdde2 vdd engclk fr_b_tx d_cs0 fr_b_ pcsa2 vddeh3 pcsb0 pcsb4 d_ta vddeh1 mseo1 jcomp rdy mseo0 vdde2 mcko mdo2 mdo0 evto evti mdo10 mdo9 mdo7 vss vdde2 vss vss vdde2 vss vss vdde2 vss vdde2 vdde2 vdde2 emios0 emios2 emios4 vdd33_1 d_add16 d_add17 d_cs3 d_cs2 vdde2 vdde2 vdde2 vdde2 d_add9 d_add10 d_add11 d_we1 d_add15 d_add14 d_add13 d_add12 d_add20 d_add19 d_add18 mdo3 mdo11 mdo12 tdi souta sckb pcsb3 pcsa3 pcsb2 d_add22 d_add25 d_add28 d_add24 d_add27 p r v w y aa ab ac ad ae af t u p r v w y aa ab ac ad ae af t u 12345678910111213 12345678910111213 tx_en tx_en d_clkout vdde2 mdo6 mdo5 mdo4 mdo8 mdo1 soutb vdd33_1 mdo15 mdo14 mdo13 vss vdde8 vdd33_4 vdde9 pcsa5 tms sinb scka vdd tdo tck vdde9 vss d_add29 d_cs1 d_add21 vdde9 emios1 mpc5674f microcontroller data sheet, rev. 9 pin assignments freescale semiconductor 18 figure 15. mpc5674f 516-ball tepbga (4 of 4) mpc5674f 516-ball tepbga (as viewed from top through the package) (4 of 4) pcsc1 vss rxdc pcsc3 vss vdd vddsyn sinc pcsc2 pcsc5 vss xtal vdd vddeh6 vddeh5 cnrxd cntxb sckc cntxd cnrxa pcsc0 cnrxc cntxa vdd etpub12 etpub14 etpub8 etpub10 etpub2 etpub0 etpub4 etpub5 etpub6 etpub16 etpub7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss emios7 emios6 emios13 emios12 emios10 emios16 emios15 emios18 emios21 emios28 emios27 emios26 tcrclkb vdde10 d_oe d_ale d_rd_wr etpub13 d_dat0 d_dat1 etpub9 etpub15 etpub3 etpub17 etpub11 etpub23 etpub1 etpub22 etpub21 emios8 emios22 emios24 p r v w y aa ab ac ad ae af t u 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 p r v w y aa ab ac ad ae af t u cnrxb vddreg vdd33_3 etpub28 vsssyn emios23 emios31 vss vdde10 vdd33_4 vdd etpub30 vsssfl extal vdde9 vss vdde9 vdde9 vdde9 emios11 emios17 emios19 emios29 etpub26 etpub27 etpub24 regctl etpub31 vddeh4 txdc vddeh5 soutc cntxc pcsc4 emios5 emios9 emios20 emios14 emios25 emios30 etpub20 etpub19 etpub18 regsel etpub29 etpub25 pin assignments mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 19 3.4 signal properties and muxing see appendix a, signal properties and muxing , for a listing and description of the pin functions and properties. mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 20 4 electrical characteristics this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for the mpc5674f. the electrical specifications are preliminary and are from prev ious designs, design simulations, or initial evaluation. these specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon th ese specifications will be met. finalized speci fications will be published after complete characterization and device qualification s have been completed. 4.1 maximum ratings table 3. absolute maximum ratings 1 spec characteristic symbol min max unit 1 1.2 v core supply voltage v dd ?0.3 2.0 2 v 2 sram standby voltage v stby ?0.3 6.4 3,4 v 3 clock synthesizer voltage v ddsyn ?0.3 5.3 4,5 v 4 i/o supply voltage (i/o buffers and predrivers) v dd33 ?0.3 5.3 4,5 v 5 analog supply voltage (reference to v ssa 6 )v dda 7 ?0.3 6.4 3,4 v 6 i/o supply voltage (fast i/o pads) v dde ?0.3 5.3 4,5 v 7 i/o supply voltage (medium i/o pads) v ddeh ?0.3 6.4 3,4 v 8 voltage regulator input supply voltage v ddreg ?0.3 6.4 3,4 v 9 analog reference high voltage (reference to v rl 8 )v rh 9 ?0.3 6.4 3,4 v 10 v ss to v ssa 8 differential voltage v ss ?v ssa ?0.1 0.1 v 11 v ref differential voltage v rh ?v rl ?0.3 6.4 3,4 v 12 v rl to v ssa differential voltage v rl ?v ssa ?0.3 0.3 v 13 v dd33 to v ddsyn differential voltage v dd33 ?v ddsyn ?0.1 0.1 v 14 v sssyn to v ss differential voltage v sssyn ?v ss ?0.1 0.1 v 15 maximum digital input current 10 (per pin, applies to all digital pins) i maxd ?3 11 3 11 ma 16 maximum analog input current 12 (per pin, applies to all analog pins) i maxa ? 3 7 3 7,11 ma 17 maximum operating temperature range 13 ? die junction temperature t j ?40.0 150.0 o c 18 storage temperature range t stg ?55.0 150.0 o c 19 maximum solder temperature 14 pb-free package snpb package t sdr ? ? 260.0 245.0 o c 20 moisture sensitivity level 15 msl ? 3 ? electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 21 4.2 thermal characteristics 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stre ss beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 2.0 v for 10 hours cumulative time, 1.2v +10% for time remaining. 3 6.4 v for 10 hours cumulative time, 5.0v +10% for time remaining. 4 voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 5.3 v for 10 hours cumulative time, 3.3v +10% for time remaining. 6 mpc5674f has two analog power supply pins on the pinout: vdda_a and vdda_b. 7 mpc5674f has two analog ground supply pins on the pinout: vssa_a and vssa_b. 8 mpc5674f has two analog low reference voltage pins on the pinout: vrl_a and vrl_b. 9 mpc5674f has two analog high reference voltage pins on the pinout: vrh_a and vrh_b. 10 total injection current for all pins must not exceed 25 ma at maximum operating voltage. 11 injection current of 5 ma allowed for lim ited duration for analog (adc) pads and digital 5 v pads. the maximum accumulated time at this current shall be 60 hours. this includes an assumption of a 5.25 v maximum analog or v ddeh supply when under this stress condition. 12 total injection current for all analog input pins must not exceed 15 ma. 13 lifetime operation at these specif ication limits is not guaranteed. 14 solder profile per cdf-aec-q100. 15 moisture sensitivity per jedec test method a112. table 4. thermal characteristics, 416-pin tepbga package 1 1 thermal characteristics are targets based on simu lation that are subject to change per device characterization. this data is preliminary based on similar package used on other devices. characteristic symbol value unit junction to ambient 2,3 natural convection (single layer board) 2 junction temperature is a function of on-chip po wer dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 3 per jedec jesd51-2 with the single layer board ho rizontal. board meets jesd51-9 specification. r ? ja 24 c/w junction to ambient 2,4 natural convection (four layer board 2s2p) 4 per jedec jesd51-6 with the board horizontal. r ? ja 18 c/w junction to ambient (@200 ft./min., single layer board) r ? jma 19 c/w junction to ambient (@200 ft./min., four layer board 2s2p) r ? jma 14 c/w junction to board 5 5 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. r ? jb 9c/w junction to case 6 6 indicates the average thermal resistance between t he die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperat ure used for the case temperature. r ? jc 6c/w junction to package top 7 natural convection 7 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. ? jt 2c/w mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 22 table 5. thermal characteristics, 516-pin tepbga package 1 1 thermal characteristics are targets based on simu lation that are subject to change per device characterization. this data is preliminary based on similar package used on other devices. characteristic symbol value unit junction to ambient 2,3 natural convection (single layer board) 2 junction temperature is a function of on-chip po wer dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 3 per jedec jesd51-2 with the single layer board ho rizontal. board meets jesd51-9 specification. r ? ja 25 c/w junction to ambient 2,4 natural convection (four layer board 2s2p) 4 per jedec jesd51-6 with the board horizontal. r ? ja 18 c/w junction to ambient (@200 ft./min., single layer board) r ? jma 20 c/w junction to ambient (@200 ft./min., four layer board 2s2p) r ? jma 15 c/w junction to board 5 5 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. r ? jb 10 c/w junction to case 6 6 indicates the average thermal resistance between t he die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperat ure used for the case temperature. r ? jc 6c/w junction to package top 7 natural convection 7 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. ? jt 2c/w table 6. thermal characteristics, 324-pin package 1 1 thermal characteristics are targets based on simu lation that are subject to change per device characterization. this data is preliminary based on similar package used on other devices. mpc5674f thermal characteristic symbol value unit junction to ambient 2, 3 , natural convection (one-layer board) 2 junction temperature is a function of on-chip pow er dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 3 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. r ? ja 29 c/w junction to ambient 1, 4 , natural convection (four-layer board 2s2p) 4 per jedec jesd51-6 with the board horizontal. r ? ja 19 c/w junction to ambient (@200 ft./min., one-layer board) r ? jma 23 c/w junction to ambient (@200 ft./min., four-layer board 2s2p) r ? jma 16 c/w junction to board 5 (four-layer board 2s2p) 5 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r ? jb 10 c/w junction to case 6 r ? jc 7c/w junction to package top 7 , natural convection ? jt 2c/w electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 23 4.2.1 general notes for specification s at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: t j =t a + (r ? ja * p d ) eqn. 1 where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient th ermal resistance is an industry st andard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for pack ages such as the tepbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal re sistance is expressed as the sum of a junc tion to case thermal resistance and a case to ambient thermal resistance: r ? ja =r ? jc + r ? ca eqn. 2 where: r ? ja = junction to ambient thermal resistance ( o c/w) r ? jc = junction to case thermal resistance ( o c/w) r ? ca = case to ambient thermal resistance ( o c/w) r ? jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of th e heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in th e application when heat sink s are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j =t t + ( ? jt x p d ) eqn. 3 where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the 6 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 me thod 1012.1) with the cold plate temperatur e used for the case temperature. 7 thermal characterization parameter indicating the te mperature difference bet ween package top and the junction temperature per jedec jesd51-2. mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 24 package. a small amount of epoxy is placed over the thermocoup le junction and over about 1 mm. of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 (408) 943-6900 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. ? c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedi ngs of semitherm, san diego, 1998, pp. 47-54. ? g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53-58, march 1998. ? b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of se mitherm, san diego, 1999, pp. 212-220. 4.3 emi (electromagnetic in terference) characteristics to find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for ?radiated emissi ons.? the following tables list the values of the device's radiated emissions operating behaviors. table 7. emc radiated emissions operating behaviors: 416 bga symbol description conditions f osc f sys frequency band (mhz) level (max.) unit notes v re_tem radiated emissions, electric field and magnetic field v dd = 1.2 v v dde = 3.3 v v ddeh = 5 v t a = 25 c 416 bga ebi off clk on fm off 40 mhz crystal 264 mhz (f ebi_cal =66 mhz) 0.15?50 26 db ? v 1 1 determined according to iec standard 61967-2, measurement of radiated emissions?tem cell and wideband tem cell method, and sae standard j1752-3, measurement of radiated emissions from integrated circuits?tem/wideband tem (gtem) cell method. 50?150 30 150?500 34 500?1000 30 iec and sae level i 2 2 i = 36 db ? v ? 1, 3 3 specified according to annex d of iec standard 61967-2, measurement of radiated emissions?tem cell and wideband tem cell method, and appendix d of sae standard j1752-3, meas urement of radiated em issions from integrated circuits?tem/wideband tem (gtem) cell method. v re_tem radiated emissions, electric field and magnetic field v dd = 1.2 v v dde = 3.3 v v ddeh = 5 v t a = 25 c 416 bga ebi off clk off fm on 4 40 mhz crystal 264 mhz (f ebi_cal =66 mhz) 0.15?50 24 db ? v 1 50?150 25 150?500 25 500?1000 21 iec and sae level k 5 ? 1,3 electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 25 4.4 esd characteristics 4.5 pmc/por/lvi electrical specifications note: for adc internal resource measurements, see ta b l e 2 0 in section 4.9.1, ?adc internal resource measurements .? 4 ?fm on? = fm depth of 2% 5 k = 30 db ? v table 8. emc radiated emissions operating behaviors: 516 bga symbol description conditions f osc f sys frequency band (mhz) level (max.) unit notes v re_tem radiated emissions, electric field and magnetic field v dd = 1.2 v v dde = 3.3 v v ddeh = 5 v t a = 25 c 516 bga ebi on clk on fm off 40 mhz crystal 264 mhz (f ebi_cal =66 mhz) 0.15?50 40 db ? v 1 1 determined according to iec standard 61967-2, measurement of radiated emissions?tem cell and wideband tem cell method, and sae standard j1752-3, measurement of radiated emissions from integrated circuits?tem/wideband tem (gtem) cell method. 50?150 48 150?500 48 500?1000 47 iec and sae level g 2 2 g = 48 db ? v ? 1, 3 3 specified according to annex d of iec standard 61967-2, measurement of radiated emissions?tem cell and wideband tem cell method, and appendix d of sae standard j1752-3, meas urement of radiated em issions from integrated circuits?tem/wideband tem (gtem) cell method. v re_tem radiated emissions, electric field and magnetic field v dd = 1.2 v v dde = 3.3 v v ddeh = 5 v t a = 25 c 516 bga ebi on clk on fm on 4 4 ?fm on? = fm depth of 2% 40 mhz crystal 264 mhz (f ebi_cal =66 mhz) 0.15?50 40 db ? v 1 50?150 44 150?500 41 500?1000 36 iec and sae level g 2 ? 1, 3 table 9. esd ratings 1,2 1 all esd testing is in conformity with cdf-aec-q1 00 stress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless sp ecified otherwise in the device specification. spec characteristic symbol value unit 1 esd for human body model (hbm) v hbm 2000 v 2 esd for charged device model (cdm) v cdm 750 (corners) 500 (other) v mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 26 note in the following table, "unt rimmed? means ?at reset" and "trimmed? means ?after reset". table 10. pmc operating conditions name parameter condition min typ max unit note v ddreg supply voltage vddreg 5v nominal ldo5v / smps5v mode 4.5 5 5.5 v 1 1 voltage should be higher than maximum v lvdreg to avoid lvd event v ddreg supply voltage vddreg 3v nominal ldo3v mode 3.0 3.3 3.6 v 1 v dd33 supply voltage vddsyn / v dd33 3.3v nominal ldo3v mode 3.0 3.3 3.6 v 2 2 applies to both v dd33 (flash supply) and vddsyn (pll supply) pads. voltage should be higher than maximum v lvd33 to avoid lvd event v dd core supply voltage ? 1.14 1.2 1.32 v 3 3 voltage should be higher than maximum v lvd12 to avoid lvd event table 11. pmc electrical specifications id name parameter min typ max unit 1v bg nominal bandgap reference voltage 0.608 0.620 0.632 v 1a ? untrimmed bandgap reference voltage v bg ? 5% v bg v bg + 5% v 2v dd12out nominal vrc regulated 1.2v output vdd ? 1.27 ? v 2a ? untrimmed vrc 1.2v output variation before band gap trim (unloaded) note: voltage should be higher than maximum v lvd12 to avoid lvd event v dd12out ? 14% v dd12out v dd12out +10% v 2b ? trimmed vrc 1.2v output variation after band gap trim (regctl load max. 20ma, vdd load max. 1a) 1 v dd12out ? 10% v dd12out v dd12out + 5% v 2c v stepv12 trimming step v dd12out ?10?mv 3v porc por rising vdd 1.2v ? 0.7 ? v 3a ? por vdd 1.2v variation v porc ? 30% v porc v porc + 30% 3b ? por 1.2v hysteresis ? 75 ? mv 4v lvd12 nominal rising lvd 1.2v note: ~v dd12out 0.87 ?1.100? v 4a ? untrimmed lvd 1.2v variation before band gap trim note: rising vdd v lvd12 ? 6% v lvd12 v lvd12 + 6% v 4b ? trimmed lvd 1.2v variation after band gap trim rising vdd v lvd12 ? 3% v lvd12 v lvd12 + 3% v electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 27 4c ? lvd 1.2v hysteresis 15 20 25 mv 4d v lvdstep12 trimming step lvd 1.2v ? 10 ? mv 5i regctl vrc dc current output on regctl ? ? 20 ma 6 ? voltage regulator 1.2v current consumption vddreg ?3?ma 7v dd33out nominal v reg 3.3v output ? 3.3 ? v 7a ? untrimmed v reg 3.3v output variation before band gap trim (unloaded) note: rising vddsyn v dd33out ? 6% v dd33out v dd33out + 10% v 7b ? trimmed v reg 3.3v output variation after band gap trim (max. load 80ma) v dd33out ? 5% v dd33out v dd33out + 10% v 7c v stepv33 trimming step vddsyn ? 30 ? mv 8v lvd33 nominal rising lvd 3.3v note: ~v dd33out 0.872 ?2.950? v 8a ? untrimmed lvd 3.3v variation before band gap trim note: rising vddsyn v lvd33 ? 5% v lvd33 v lvd33 + 5% v 8b ? trimmed lvd 3.3v variation after bad gap trim note: rising vddsyn v lvd33 ? 3% v lvd33 v lvd33 + 3% v 8c ? lvd 3.3v hysteresis ? 30 ? mv 8d v lvdstep33 trimming step lvd 3.3v ? 30 ? mv 9i dd33 v reg = 4.5 v, max dc output current v reg = 4.25 v, max dc output current, crank condition note: max current supplied by vddsyn that does not cause it to drop below v lvd33 ? ? ? ? 80 40 ma ma 10 ? voltage regulator 3.3v current consumption vddreg note: except i dd33 ?2?ma 11 v porreg por rising on vddreg ? 2.00 ? v 11a ? por vddreg variation v porreg ? 30% v porreg v porreg + 30% v 11b ? por vddreg hysteresis ? 250 ? mv 12 v lvdreg nominal rising lvd vddreg (ldo3v / ldo5v mode) ?2.950? v 12a ? untrimmed lvd vddreg variation before band gap trim note: rising vddreg v lvdreg ? 5% v lvdreg v lvdreg + 5% v 12b ? trimmed lvd vddreg variation after band gap trim note: rising vddreg v lvdreg ? 3% v lvdreg v lvdreg + 3% v table 11. pmc electrical specifications (continued) id name parameter min typ max unit mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 28 12c ? lvd vddreg hysteresis (ldo3v / ldo5v mode) ?30?mv 12d v lvdstepreg trimming step lvd vddreg (ldo3v / ldo5v mode) ?30?mv 13 v lvdreg nominal rising lvd vddreg (smps5v mode) ?4.360? v 13a ? untrimmed lvd vddreg variation before band gap trim note: rising vddreg v lvdreg ? 5% v lvdreg v lvdreg + 5% v 13b ? trimmed lvd vddreg variation after band gap trim note: rising vddreg v lvdreg ? 3% v lvdreg v lvdreg + 3% v 13c ? lvd vddreg hysteresis (smps5v mode) ?50?mv 13d v lvdstepreg trimming step lvd vddreg (smps5v mode) ?50?mv 14 v lvda nominal rising lvd vdda ? 4.60 ? v 14a ? untrimmed lvd vdda variation before band gap trim v lvda ? 5% v lvda v lvda + 5% v 14b ? trimmed lvd vdda variation after band gap trim v lvda ? 3% v lvda v lvda + 3% v 14c ? lvd vdda hysteresis ? 150 ? mv 14d v lvdastep trimming step lvd vdda ? 20 ? mv 15 ? smps regulator output resistance note: pulup to vddreg when high, pulldown to vssreg when low. ?1525ohm 16 ? smps regulator clock frequency (after reset) 1.0 1.5 2.4 mhz 17 ? smps regulator overshoot at start-up 2 ?1.321.4v 18 ? smps maximum output current ? 1.0 ? a 19 ? voltage variation on current step 2 (20% to 80% of maximum current with 4 usec constant time) ??0.1v 1 vrc linear regulator is capable of sourcing a curr ent up to 20 ma and sinking a current up to 500 ? a. when using the recommended ballast transistor the maximum output current provid ed by the voltage regulator vrc/ballast to the vdd core voltage is up to 1a. 2 parameter cannot be tested; this value is based on simulation and characterization. table 11. pmc electrical specifications (continued) id name parameter min typ max unit electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 29 4.6 power up/down sequencing there is no power sequencing required among power sources dur ing power up and power down in order to operate within specification as long as the following two rules are met: ? when vddreg is tied to a nominal 3.3v supply, vdd33 and vddsyn must be both shorted to vddreg. ? when vddreg is tied to a 5v supply, vdd33 and vddsyn must be tied together and shall be powered by the internal 3.3v regulator. the recommended power supply behavior is as follows: use 25 v/ millisecond or slower rise time for all supplies. power up each v dde /v ddeh first and then power up v dd . for power down, drop v dd to 0 v first, and then drop all v dde /v ddeh supplies. there is no limit on the fall time for the power supplies. although there are no power up/down sequencing requirements to prevent issues like latch-up, ex cessive current spikes, etc., the state of the i/o pins during power up/down varies according to table 12 and table 13 . 4.6.1 power-up if v dde /v ddeh is powered up first, then a threshold de tector tristates all drivers connected to v dde /v ddeh . there is no limit to how long after v dde /v ddeh powers up before v dd must power up. if there are multiple v dde /v ddeh supplies, they can be powered up in any order. for each v dde /v ddeh supply not powered up, the drivers in that v dde /v ddeh segment exhibit the characteristics described in the next paragraph. table 12. power sequence pin states for mh and ae pads vdd vdd33 vdde mh pad mh+lvds pads 1 1 mh+lvds pads are output-only. ae/up-down pads high high high normal operation normal operation normal operation ? low high pin is tri-stated (output buffer, input buffer, and weak pulls disabled) outputs disabled pull-ups enabled, pull-downs disabled low high low output low, pin unpowered outputs disabled output low, pin unpowered low high high pin is tri-stated (output buffer, input buffer, and weak pulls disabled) outputs disabled pull-ups enabled, pull-downs disabled table 13. power sequence pin states for f and fs pads vdd vdd33 vdde f and fs pads low low high outputs disabled low high ? outputs disabled high low low outputs disabled high low high outputs disabled high high low normal operation - except no drive current and input buffer output is unknown. 1 1 the pad pre-drive circuitry will function normally but since vdde is unpowered the outputs will not drive high even th ough the output pmos can be enabled. high high high normal operation mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 30 if v dd is powered up first, then all pads are loaded through the drain diodes to v dde /v ddeh . this presents a heavy load that pulls the pad down to a diode above v ss . current injected by extern al devices connected to the pads must meet the current injection specification. there is no limit to how long after v dd powers up before v dde /v ddeh must power up. the rise times on the power supplies ar e to be no faster than 25 v/millisecond. 4.6.2 power-down if v dd is powered down first, then a ll drivers are tris tated. there is no limit to how long after v dd powers down before v dde /v ddeh must power down. if v dde /v ddeh is powered down first, then all pads are loaded through the drain diodes to v dde /v ddeh . this presents a heavy load that pulls the pad down to a diode above v ss . current injected by exte rnal devices connected to the pads must meet the current injection specificat ion. there is no limit to how long after v dde /v ddeh powers down before v dd must power down. there are no limits on the fall times for the power supplies. 4.6.3 power sequencing and por dependent on v dda during power up or down, v dda can lag other supplies (of magnitude greater than v ddeh /2) within 1 v to prevent any forward-biasing of device di odes that causes leakage cu rrent and/or por. if the voltage difference between v dda and v ddeh is more than 1 v, the following will result: ? triggers por (adc monitors on v ddeh1 segment which powers the reset pin) if the leakage curr ent path created, when v dda is sufficiently low, causes sufficient voltage drop on v ddeh1 node monitored crosses low-voltage detect level. ?if v dda is between 0?2 v, powering all the other segments (especially v ddeh1 ) will not be sufficient to get the part out of reset. ? each v ddeh will have a leakage current to v dda of a magnitude of ((v ddeh ?v dda ? 1 v(diode drop)/200 kohms) up to (v ddeh /2 = v dda +1v). ? each v dd has the same behavior; however, the leakage will be small even though there is no current limiting resistor since v dd = 1.32 v max. 4.7 dc electrical specifications table 14. dc electrical specifications spec characteristic symbol min max unit 1 core supply voltage (external regulation) v dd 1.14 1.32 1,2 v 1a core supply voltage (internal regulation) 3 v dd 1.08 1.32 v 2 i/o supply voltage (fast i/o pads) v dde 3.0 3.6 1,4 v 3 i/o supply voltage (medium i/o pads) v ddeh 3.0 5.25 1,5 v 4 3.3 v i/o buffer voltage v dd33 3.0 3.6 1,4 v 5 analog supply voltage v dda 4.75 5.25 1,5 v 6a sram standby voltage keep-out range: 1.2v?2v v stby_low 0.95 6 1.2 v 6b sram standby voltage keep-out range: 1.2v?2v v stby_high 26v 7 voltage regulator control input voltage 7 v ddreg 2.7 8 5.5 1,5 v electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 31 8 clock synthesizer operating voltage 9 v ddsyn 3.0 3.6 1,4 v 9 fast i/o input high voltage hysteresis enabled hysteresis disabled v ih_f 0.65 v dde 0.55 v dde v dde +0.3 v 10 fast i/o input low voltage hysteresis enabled hysteresis disabled v il_f v ss ?0.3 0.35 v dde 0.40 v dde v 11 medium i/o input high voltage hysteresis enabled hysteresis disabled v ih_s 0.65 v ddeh 0.55 v ddeh v ddeh +0.3 v 12 medium i/o input low voltage hysteresis enabled hysteresis disabled v il_s v ss ?0.3 0.35 v ddeh 0.40 v ddeh v 13 fast i/o input hysteresis v hys_f 0.1 v dde ?v 14 medium i/o input hysteresis v hys_s 0.1 v ddeh ?v 15 analog input voltage v indc v ssa ?0.1 v dda +0.1 v 16 fast i/o output high voltage 10 v oh_f 0.8 v dde ?v 17 medium i/o output high voltage 11 v oh_s 0.8 v ddeh ?v 18 fast i/o output low voltage 10 v ol_f ?0.2v dde v 19 medium i/o output low voltage 11 v ol_s ?0.2v ddeh v 20 load capacitance (fast i/o) 12 dsc(pcr[8:9]) = 0b00 dsc(pcr[8:9]) = 0b01 dsc(pcr[8:9]) = 0b10 dsc(pcr[8:9]) = 0b11 c l ? ? ? ? 10 20 30 50 pf pf pf pf 21 input capacitance (digital pins) c in ?7pf 22 input capacitance (analog pins) c in_a ?10pf 24 operating current 1.2 v supplies @ f sys =264mhz v dd @1.32 v v stby 13 @1.2 v and 85 o c v stby @6.0 v and 85 o c i dd i ddstby i ddstby6 ? ? ? 850 0.10 0.15 ma ma ma 25 operating current 3.3 v supplies @ f sys =264mhz v dd33 14 v ddsyn i dd33 i ddsyn ? ? note 14 7 15 ma ma 26 operating current 5.0 v supplies @ f sys =264mhz v dda analog reference supply current (transient) v ddreg i dda i ref i reg ? ? ? 50 16 1.0 22 ma ma ma table 14. dc electrical sp ecifications (continued) spec characteristic symbol min max unit mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 32 27 operating current v dde /v ddeh 17 supplies v dde2 v ddeh1 v ddeh3 v ddeh4 v ddeh5 v ddeh6 v ddeh7 i dd2 i dd1 i dd3 i dd4 i dd5 i dd6 i dd7 ? ? ? ? ? ? ? note 17 ma ma ma ma ma ma ma 28 fast i/o weak pull up/down current 18 3.0 v?3.6 v i act_f 42 158 ? a 29 medium i/o weak pull up/down current 19 3.0 v?3.6 v 4.5 v?5.5 v i act_s 15 35 95 200 ? a ? a 30 i/o input leakage current 20 i inact_d ?2.5 2.5 ? a 31 dc injection current (per pin) i ic ?1.0 1.0 ma 32 analog input current, channel off 21 , an[0:7], an38, an39 analog input current, channel off, all other analog inputs an[x] i inact_a ?250 ?150 250 150 na na 33 v ss differential voltage v ss ?v ssa ?100 100 mv 34 analog reference low voltage v rl v ssa v ssa +100 mv 35 v rl differential voltage v rl ?v ssa ?100 100 mv 36 analog reference high voltage v rh v dda ?100 v dda mv 37 v ref differential voltage v rh ?v rl 4.75 5.25 v 38 v sssyn to v ss differential voltage v sssyn ?v ss ?100 100 mv 39 operating temperature range?ambient (packaged) t a (t l to t h ) ?40.0 125.0 ? c 40 slew rate on power supply pins ? ? 25 v/ms 41 weak pull-up/down resistance 22 , 200 k option r pupd200k 130 280 k ? 42 weak pull-up/down resistance 22 , 100 k option r pupd100k 65 140 k ? 43 weak pull-up/down resistance 22 , 5 k option r pupd5k 1.4 7.5 k ? 44 pull-up/down resistance matching ratios 23 (100k/200k) r pupdmtch ?2.5 +2.5 % 1 voltage overshoots during a high-to-low or low-to-hi gh transition must not exceed 10 seconds per instance. 2 2.0 v for 10 hours cumulative time , 1.2 v +10% for time remaining. 3 assumed with dc load. 4 5.3 v for 10 hours cumulative time , 3.3 v +10% for time remaining. 5 6.4 v for 10 hours cumulative time , 5.0 v +10% for time remaining. 6 v stby below 0.95 v the ram will not retain states, but will be operational. v stby can be 0 v when bypass standby mode. 7 regulator is functional with de rated performance, with s upply voltage dow n to 4.0 v for system with v ddreg =4.5v (min). 8 2.7 v minimum operating voltage allowed during vehicle crank for system with v ddreg = 3.0 v (min). normal operating voltage should be either v ddreg = 3.0 v (min) or 4.5 v (min) depending on th e user regulation voltage system selected. 9 required to be supplied when 3.3 v regulator is disabled. see section 4.5, ?pmc/por/lvi electrical specifications.? table 14. dc electrical sp ecifications (continued) spec characteristic symbol min max unit electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 33 4.7.1 i/o pad current specifications the power consumption of an i/o segment is dependent on th e usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin current can be calculated from table 15 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 15 . the ac timing of these pads are described in the section 4.11.2, ?pad ac specifications .? 10 i oh_f = {16,32,47,77} ma and i ol_f = {24,48,71,115} ma for {00,01,10,11} drive mode with v dde = 3.0 v. this spec is for characterization only. 11 i oh_s = {11.6} ma and iol_s = {17.7} ma for {medium} i/o with v dde =4.5v; i oh_s = {5.4} ma and iol_s = {8.1} ma for {medium} i/o with v dde = 3.0 v. these specs are for characterization only. 12 applies to d_clkout, external bus pins, and nexus pins. 13 v stby current specified at 1.0 v at a junction temperature of 85 o c. v stby current is 700 a maximum at a junction temperature of 150 o c. 14 power requirements for the v dd33 supply depend on the frequency of operation and load of all i/o pins, and the voltages on the i/o segments. 15 this value is a target that is subject to change. 16 this value allows a 5 v reference to supply adc + ref. 17 power requirements for each i/o segment depend on the frequency of operation and load of the i/o pins on a particular i/o segment, and the voltage of the i/o segment. see section 4.7.1, ?i/o pad current specifications ,? for information on i/o pad power. also refer to table 15 for values to calculate power dissipation for sp ecific operation. the total power consumption of an i/o segment is the sum of the individual power consumptions for each pin on the segment. 18 absolute value of current, measured at v il and v ih . 19 absolute value of current, measured at v il and v ih . 20 weak pull up/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types f and mh. 21 maximum leakage occurs at maximum operat ing temperature. leakage cu rrent decreases by approximately one-half for each 8to12 o c, in the ambient temperat ure range of 50 to 125 o c. applies to pad types ae and ae/up-down. see appendix a, signal properties and muxing. 22 this programmable option applies only to eqadc differential input channels and is used for biasing and sensor diagnostics 23 pull-up and pull-down resistances are both enabled and settings are equal. table 15. v dde /v ddeh i/o pad average dc current 1 spec pad type symbol frequency (mhz) load 2 (pf) voltage (v) drive/slew rate select current (ma) 1medium i drv_mh 50 50 5.25 11 16.0 2 20 505.2501 6.3 3 3.0 50 5.25 00 1.1 4 2.0 200 5.25 00 2.4 5fast i drv_fc 66 10 3.6 00 7.4 666203.60110.5 766303.61012.3 866503.61135.2 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 34 9 fast w/ slew control i drv_fsr 66 50 3.6 11 12.7 10 50 50 3.6 10 6.7 11 33.33 50 3.6 01 4.2 12 20 50 3.6 00 2.6 13 20 200 3.6 00 9.1 1 these are average idde numbers for worst case pvt fr om simulation. currents apply to output pins only. 2 all loads are lumped. table 15. v dde /v ddeh i/o pad average dc current 1 (continued) spec pad type symbol frequency (mhz) load 2 (pf) voltage (v) drive/slew rate select current (ma) electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 35 4.7.2 lvds pad specifications lvds pads are implemented to support th e msc (microsecond channel) protocol, whic h is an enhanced f eature of the dspi module. 4.8 oscillator and fmpll el ectrical characteristics table 16. dspi lvds pad specification # characteristic symbol condition min. value typ. value max. value unit data rate 1 data frequency f lvdsclk ??50?mhz driver specs 2 differential output voltage v od src=0b00 or 0b11 150 ? 400 mv src=0b01 90 ? 320 src=0b10 160 ? 480 3 common mode voltage (lvds), vos v os ? 1.06 1.2 1.39 v 4 rise/fall time t r /t f ??2?ns 5 propagation delay (low to high) t plh ??4?ns 6 propagation delay (high to low) t phl ??4?ns 7 delay (h/l), sync mode t pdsync ??4?ns 8 delay, z to normal (high/low) t dz ??500?ns 9 diff skew itphla-tplhbi or itplhb-tphlai t skew ???0.5ns termination 10 trans. line (differential zo) ? ? 95 100 105 ohms 11 temperature ? ? ?40 ? 150 ? c table 17. fmpll electrical specifications 1 (v ddsyn = 3.0 v to 3.6 v, v ss =v sssyn =0v, t a =t l to t h ) spec characteristic symbol min max unit 1 pll reference frequency range 2 (normal mode) crystal reference (pllcfg2 = 0b0) crystal reference (pllcfg2 = 0b1) external reference (pllcfg2 = 0b0) external reference (pllcfg2 = 0b1) f ref_crystal f ref_crystal f ref_ext f ref_ext 8 16 8 16 20 40 3 20 40 mhz 2 loss of reference frequency 4 f lor 100 1000 khz 3 self clocked mode frequency 5 f scm 416mhz 4 pll lock time 6 t lpll ? < 400 ? s mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 36 5 duty cycle of reference 7 t dc 40 60 % 6 frequency un-lock range f ul ?4.0 4.0 % f sys 7 frequency lock range f lck ?2.0 2.0 % f sys 8 d_clkout period jitter 8, 9 measured at f sys max cycle-to-cycle jitter c jitter ?5 5 %f clkout 9 peak-to-peak frequency modulation range limit 10,11 (f sys max must not be exceeded) c mod 04%f sys 10 fm depth tolerance 12 c mod_err ?0.25 0.25 %f sys 11 vco frequency f vco 192 600 mhz 12 modulation rate limits 13 f mod 0.400 1 mhz 13 predivider output frequency range 14 f prediv 410mhz 1 all values given are initial design targets and subject to change. 2 crystal and external reference frequency limits depend on device re lying on pll to lock prior to release of reset, default prediv/eprediv, mfd/emfd default settings, and vco frequency range. absolute minimum loop frequency is 4 mhz. 3 upper tolerance of less than 1% is allowed on 40mhz crystal. 4 ?loss of reference frequency? is the refer ence frequency detected internally, which tr ansitions the pll into self clocked mode. 5 self clocked mode frequency is the frequency that the pl l operates at when the reference frequency falls below f lor . this frequency is measured at d_clkout. a default rfd value of (0x05) is used in scm mode, and the programmed mfd and rfd values have no effect 6 this specification applies to the period required for the pll to re-lock after changing the mfd frequency control bits in the synthesizer control register (syncr). from power up with crystal oscillator refere nce, lock time will be additive with crystal startup time. 7 for flexray operation, duty cycle requirements are higher. 8 jitter is the average deviation from t he programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered su pplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. d_clkout divider set to divide-by-2. 9 values are with frequency modulation disabled. if frequ ency modulation is enabled, jitter is the sum of c jitter +c mod . 10 modulation depth selected must not result in f pll value greater than the f pll maximum specified value. 11 maximum and minimum variation from programmed modulation dep th is pending characterization. depth settings available in control register are: 2%, 3%, and 4% peak-to-peak. 12 depth tolerance is the programmed modulation depth 0.25% of f sys . violating the vco min/max range may prevent the system from exiting reset. 13 modulation rates less than 400 khz will result in exceedingly long fm calibration durations. modulation rates greater than 1 mhz will result in reduced calibration accuracy. 14 violating this range will cause the vco max/min range to be violated with the default mfd settings out of reset. table 17. fmpll electrical specifications 1 (continued) (v ddsyn = 3.0 v to 3.6 v, v ss =v sssyn =0v, t a =t l to t h ) spec characteristic symbol min max unit electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 37 4.9 eqadc electrical characteristics table 18. oscillator el ectrical specifications 1 (v ddsyn = 3.0 v to 3.6 v, v ss =v sssyn =0v, t a =t l to t h ) 1 all values given are initial design targets and subject to change. spec characteristic symbol min max unit 1 crystal mode differential amplitude 2 (min differential voltage between extal and xtal) 2 this parameter is meant for those who do not use quartz crystal s or resonators, but instead use can oscillators in crystal mode . in that case, v extal ?v xtal ? 400 mv criterion has to be met for oscilla tor?s comparator to produce output clock. v crystal_diff_amp | v extal ? v xtal | > 0.4 v ?v 2 crystal mode: internal differential amplifier noise rejection v crystal_diff_amp_nr ? | v extal ? v xtal | < 0.2 v v 3 extal input high voltage bypass mode, external reference v ihext ((v dd33 /2) + 0.4 v) ?v 4 extal input low voltage bypass mode, external reference v ilext ? (v dd33 /2) ? 0.4 v v 5xtal current 3 3 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. i xtal 13ma 6 total on-chip stray capacitance on xtal c s_xtal ? 1.5 pf 7 total on-chip stray capacitance on extal c s_extal ? 1.5 pf 8 crystal manufacturer?s recommended capacitive load c l see crystal spec see crystal spec pf 9 discrete load capacitance to be connected to extal c l_extal ? (2 c l ?c s_extal ?c pcb_extal 4 ) 4 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. pf 10 discrete load capacitance to be connected to xtal c l_xtal ? (2 c l ?c s_xtal ?c pcb_xtal 4 ) pf table 19. eqadc conversion specifications (operating) spec characteristic symbol min max unit 1 adc clock (adclk) frequency f adclk 216mhz 2 conversion cycles single ended conversion cycles 12 bit resolution single ended conversion cycles 10 bit resolution single ended conversion cycles 8 bit resolution note: differential conversion (min) is one clock cycle less than the single-ended conversion values listed here. cc 2+14 2+12 2+10 128 + 14 128 + 12 128 + 10 adclk cycles 3 stop mode recovery time 1 t sr 10 ? ? s 4 resolution 2 ?1.25 ? mv 5 inl: 8 mhz adc clock 3 inl8 ?4 4 4 4 lsb 5 6 inl: 16 mhz adc clock 3 inl16 ?8 4 8 4 lsb 7 dnl: 8 mhz adc clock 3 dnl8 ?3 4 3 4 lsb 8 dnl: 16 mhz adc clock 3 dnl16 ?3 4 3 4 lsb mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 38 9 offset error without calibration offnc 0 4 100 4 lsb 10 offset error with calibration offwc ?4 4 4 4 lsb 11 full scale gain error without calibration gainnc ?120 4 0 4 lsb 12 full scale gain error with calibration gainwc ?4 4,6 4 4,6 lsb 13 non-disruptive input injection current 7, 8, 9, 10 i inj ?3 3 m ? 14 incremental error due to injection current 11, 12 e inj ?4 4 4 4 counts 15 tue value at 8 mhz 13, 14 (with calibration) tue8 ?4 4,6 4 4,6 counts 16 tue value at 16 mhz 13, 14 (with calibration) tue16 ?8 8 counts 17 maximum differential voltage 15 (danx+ - danx-) or (danx- - danx+) pregain set to 1x setting pregain set to 2x setting pregain set to 4x setting diff max diff max2 diff max4 ? ? ? (v rh ?v rl )/2 (v rh ?v rl )/4 (v rh -v rl )/8 v v v 18 differential input common mode voltage 15 (danx- + danx+)/2 diff cmv (v rh ?v rl )/2 ?5% (v rh ?v rl )/2 +5% v 1 stop mode recovery time is the time from the setting of either of the enable bits in the adc cont rol register to the time that the adc is ready to perform conversions. delay from power up to full accuracy = 8 ms. 2 at v rh ?v rl = 5.12 v, one count = 1.25 mv without using pregain. 3 inl and dnl are tested from v rl + 50 lsb to v rh ? 50 lsb. the eqadc is guaranteed to be monotonic at 10 bit accuracy (12 bit resolution selected). 4 new design target. actual specif ication will change following characterization . margin for manufacturing has not been fully included. 5 at v rh ?v rl = 5.12 v, one lsb = 1.25 mv. 6 the value is valid at 8 mhz, it is 8 counts at 16 mhz. 7 below disruptive current conditions, the channel being stressed has conversion values of $3ff for analog inputs greater than v rh and $000 for values less than v rl . other channels are not affected by non-disruptive conditions. 8 exceeding limit may cause conversion error on stressed channels and on unstressed channels. transitions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the value specified. to determi ne the value of the required current-limiting resistor, calcula te resistance values using v posclamp =v dda + 0.5 v and v negclamp = ?0.3 v, then use the larger of the calculated values. 10 condition applies to two adjacent pins at injection limits. 11 performance expected with production silicon. 12 all channels have same 10 k ? < rs < 100 k ?? channel under test has rs = 10 k ? , i inj =i injmax ,i injmin . 13 the tue specification is always less than the sum of the in l, dnl, offset, and gain errors due to cancelling errors. 14 tue does not apply to differential conversions. 15 voltages between vrl and vrh will not cause damage to the pins . however, they may not be converted accurately if the differential voltage is above the maximum differential voltage. in addition, conversion errors may occur if the common mode voltage of the differential signal violates the dif ferential input common mode voltage specification. table 19. eqadc conversion specifications (operating) (continued) spec characteristic symbol min max unit electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 39 4.9.1 adc internal resource measurements table 20. power management control (pmc) specification spec characteristic symbol min typical max unit pmc normal mode 1 bandgap 0.62 v adc0 channel 145 v adc145 ? 0.62 ? v 2 bandgap 1.2 v adc0 channel 146 v adc146 ? 1.22 ? v 3 vreg1p2 feedback adc0 channel 147 v adc147 ? v dd /2.045 ? v 4lvd 1.2v adc0 channel 180 v adc180 ? v dd /1.774 ? v 5 vreg3p3 feedback adc0 channel 181 v adc181 ? vreg3p3 / 5.460 ? v 6lvd 3.3v adc0 channel 182 v adc182 ? vreg3p3 / 4.758 ?v 7lvd 5.0v adc0 channel 183 ? ldo mode ? smps mode v adc183 ? v ddreg / 4.758 v ddreg /7.032 ? v table 21. standby ram regula tor electrical specifications spec characteristic symbol min typ max unit normal mode 1 standby regulator output adc1 channel 194 v adc194 ? 1.2 ? v 2 standby source bias 150 mv to 360 mv (30mv increment @ vref_sel) adc1 channel 195 default value 150 mv (@vref_sel = 1 1 1) v adc195 150 ? 360 mv 3 standby brownout reference adc1 channel 195 v adc195 500 ? 850 mv mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 40 4.10 c90 flash memory electrical characteristics table 22. adc band gap referenc e / lvi electrical specifications spec characteristic symbol min typ max unit 1 4.75 lvd (from v dda ) adc1 channel 196 v adc196 ? 4.75 ? v 2 adc bandgap adc0 channel 45 adc1 channel 45 v adc45 1.171 1.220 1.269 v table 23. temperature sensor electrical specifications spec characteristic symbol min typ max unit 1slope ?40 ? c to 100 ? c 1.0 ? c 100 ? c to 150 ? c 1.6 ? c adc0 channel 128 adc1 channel 128 v sadc128 1 1 slope is the measured voltage change per c. ? 5.8 ? mv/ ? c 2 accuracy ?40 ? c to 150 ? c adc0 channel 128 adc1 channel 128 ?? 10.0 ? ? c table 24. flash program and erase specifications spec characteristic symbol min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 o c. initial max 2 2 initial factory condition: ? 100 program/erase cycles, 25 o c, typical supply voltage, 80 mhz minimum system frequency. max 3 3 the maximum erase time occurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. unit 1 double word (64 bits) program time 4 4 program times are actual hardware programming times and do not include software overhead. t dwprogram ? 38 ? 500 ? s 2 page program time 4,5 5 page size is 128 bits (4 words). t pprogram ? 45 160 500 ? s 3 16 kb block pre-program and erase time t 16kpperase ? 270 1000 5000 ms 4 64 kb block pre-program and erase time t 64kpperase ? 800 1800 5000 ms 5 128 kb block pre-program and erase time t 128kpperase ? 1500 2600 7500 ms 6 256 kb block pre-program and erase time t 256kpperase ? 3000 5200 15000 ms electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 41 table 26 shows the platform flash co nfiguration register 1 (pfcpr1) settings versus frequency of operation. refer to the device reference manual for definitions of these bit fields. table 25. flash eeprom module life spec characteristic symbol min typical 1 1 typical endurance is evaluated at 25 c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typical e ndurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . unit 1 number of program/erase cycles per block for 16 kb and 64 kb blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 2 number of program/erase cycles per block for 128 kb and 256 kb blocks over the operating temperature range (t j ) p/e 1,000 100,000 cycles 3 minimum data retention at 85 c ambient temperature 2 blocks with 0?1,000 p/e cycles blocks with 1,001?10,000 p/e cycles blocks with 10,001?1 00,000 p/e cycles 2 ambient temperature averaged over duration of application, not to e xceed product operating temperature range. retention 20 10 5 ? ? ? years table 26. pfcpr1 settings vs. frequency of operation 1 1 illegal combinations exist. use entries from the same row in this table. spec clock mode maximum frequency 2 (mhz) 2 this is the nominal maximum frequency of operation: plat form runs at f sys /2 in enhanced mode . apc = rwsc wwsc dpfen 3 3 for maximum flash performance, set to 0b1. ipfen 3 pflim 4 4 for maximum flash performance, set to 0b10. bfen 5 5 for maximum flash performance, set to 0b1. core f sys platform f platf 1 enhanced 264 mhz 6 6 this is the nominal maximum frequency of operation in enchanced mode. max speed is the maximum speed allowed including frequency modulation (fm). 270 m hz parts allow for 264 mhz system core clock(f sys )+2% fm and 132 mhz platform clock (f platf )+ 2% fm. 132 mhz 6 0b011 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 2 enhanced/ full 200 mhz 100 mhz 0b010 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 3 legacy 132 mhz 132 mhz 0b100 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 default setting after reset: 0b111 0b11 0b00 0b00 0b00 0b0 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 42 4.11 ac specifications 4.11.1 clocking the figure 16 shows the operating frequency domains of various blocks on mpc5674f. figure 16. mpc5674f block operating frequency domain diagram table 27 shows the operating frequencies of vari ous blocks depending on the device?s clocking mode configuration settings (see table 28 and table 29 for descriptions of bit settings). table 27. mpc5674f operating frequencies 1, 2 1 the values in the table are specified at: v dd = 1.02 v to 1.32 v v dde = 3.0 v to 3.6 v v ddeh = 4.5 v to 5.5 v v dd33 and v ddsyn = 3.0 v to 3.6 v t a =t l to t h . mode siu_eccr [ebdf[0:1]] 3 f sys (core) f platf (platform and all blocks except etpu) f etpu (etpu, etpu ram, and ndedi) f ebi_cal 4,5 unit enhanced 01 11 264 264 132 132 132 132 66 33 mhz full 01 11 200 200 100 100 200 200 50 25 mhz legacy 01 11 132 132 132 132 132 132 66 33 mhz pll core platform / etpu / ebi cal bus extal d_clkout f platf note: t cycsys = 1 / f sys t cyc =1 / f platf ?? 2 = divide-by-2 ? x = divide-by-x, depending on siu_sysdiv[bypass] and siu_sysdiv[sysclkdiv]. blocks / (d_clkout is not available on all packages and cannot be programmed for faster than fsys/2.) ? 2 pllcfg[0:1] siu_sysdiv[ sysclkdiv [0:1]] ipg div sel etpu div sel siu_sysdiv[ ipclkdiv [0:1]] f etpu sysdiv ? x flash ndedi div f ebi_cal siu_sysdiv[ bypass ] x = 2, 4, 8, or 16 x=1 f sys siu_eccr[ ebdf [0:1]] f periph electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 43 2 up to the maximum frequency rating of the device (refer to ta b l e 1 ). the f sys speed is the nominal maximum frequency. 270 mhz parts allow for 264 mhz system clock + 2% fm. 3 see the mpc5674f reference manual for full description as not all bit combinations are valid. 4 ebi/calibration bus is not available in all packages. 5 the ebi/calibration bus operating frequency, f ebi_cal , depends on clock divider settings of block?s max allowed frequency of operation. normally f ebi_cal =f platf /2, but can be limited to < f platf /2 in full mode. table 28. ipclkdiv settings siu_sysdiv [ipclkdiv[0:1]] mode description 00 enhanced cpu frequency is doubled (max 264mhz). platform, peripheral, and et pu clocks are 1/2 of cpu frequency 01 full cpu and etpu frequency is doubled (max 200mhz). platform and peripheral clocks are 1/2 of cpu frequency. 10 ? reserved 11 legacy cpu, etpu, platform, and peripheral?s clocks all run at same speed (max 132mhz). table 29. sysclkdiv settings siu_sysdiv [sysclkdiv[0:1]] description 00 divide by 2. 01 divide by 4. 10 divide by 8. 11 divide by 16. mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 44 4.11.2 pad ac specifications table 30. pad ac specifications (v ddeh =5.0v, v dde =3.3v) 1 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at v dd = 1.02 v to 1.32 v, v dde = 3.0 v to 3.6 v, v ddeh = 4.75 v to 5.25 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . spec pad src/dsc out delay 2,4 l ? h/h ? l (ns) 2 this parameter is supplied for reference and is not guaranteed by design and not tested. rise/fall 3,4 (ns) 3 this parameter is guaranteed by characterization before qualification rather than 100% tested. 4 delay and rise/fall are measured to 20% or 80% of the respective signal. load drive (pf) 1medium 5 5 out delay is shown in figure 17 . add a maximum of one system clock to the output delay for delay with respect to system clock. 00 152/165 70/74 50 2 205/220 96/96 200 3 01 28/34 12/15 50 4 52/59 28/31 200 5 11 12/12 5.3/5.9 50 6 32/32 22/22 200 7fast 5 00 2.5 1.2 10 801 20 910 30 10 11 50 11 fast with slew rate 00 40/40 16/16 50 12 50/50 21/21 200 13 01 13/13 5/5 50 14 19/19 8/8 200 15 10 8/8 2.4/2.4 50 16 12/12 5/5 200 17 11 5/5 1.1/1/1 50 18 8/8 2.6 2.6 19 pull up/down (3.6 v max) ? ? 7500 50 20 pull up/down (5.25 v max) ? 6000 5000/5000 50 electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 45 figure 17. pad output delay 4.12 ac timing 4.12.1 generic timing diagrams the generic timing diagrams in figure 18 and figure 19 apply to all i/o pins with pad types f and mh. see appendix a, signal properties and muxing , for the pad type for each pin. table 31. derated pad ac specifications (v ddeh =3.3v) 1 1 these are worst case values that are es timated from simulation and not tested. th e values in the table are simulated at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v ddeh = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . spec pad src/dsc out delay 2,3 l ? h/h ? l (ns) 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 delay and rise/fall are measured to 20% or 80% of the respective signal. rise/fall 4,3 (ns) 4 this parameter is guaranteed by characterizati on before qualification rather than 100% tested. load drive (pf) 1 medium 5 5 out delay is shown in figure 17 . add a maximum of one system clock to the output delay for delay with respect to system clock. 00 200/210 86/86 50 2 270/285 120/120 200 3 01 37/45 15.5/19 50 4 69/82 38/43 200 5 11 18/17 7.6/8.5 50 6 46/49 30/34 200 v dde n / 2 v oh v ol rising edge output delay falling edge output delay pad data input pad output v ddeh n / 2 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 46 figure 18. generic output delay/hold timing figure 19. generic input setup/hold timing 4.12.2 reset and configuration pin timing table 32. reset and configuration pin timing 1 1 reset timing specified at: v ddeh = 3.0 v to 5.25 v, v dd = 1.08 v to 1.32 v, t a =t l to t h . spec characteristic symbol min max unit 1 reset pulse width t rpw 10 ? t cyc 2 2 reset glitch detect pulse width t gpw 2?t cyc 2 3 pllcfg, bootcfg, wkpcfg setup time to rstout valid t rcsu 10 ? t cyc 2 4 pllcfg, bootcfg, wkpcfg hold time to rstout valid t rch 0?t cyc 2 v dde / 2 d_clkout a ? maximum output delay time b ? minimum output hold time v dde n / 2 a b i/o outputs v ddeh n / 2 v dde / 2 a b d_clkout v dde n / 2 i/o inputs a ? minimum input se tup time b ? minimum input hold time v ddeh n / 2 electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 47 figure 20. reset and configuration pin timing 4.12.3 ieee 1149.1 interface timing 2 see notes on t cyc on figure 16 and ta b l e 2 7 in section 4.11.1, ?clocking .? table 33. jtag pin ac electrical characteristics 1 spec characteristic symbol min max unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde / 2) t jdc 40 60 ns 3 tck rise and fall times (40%?70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ? 12.5 ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling edge to output valid t bsdv ?50ns 12 tck falling edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling edge to output high impedance t bsdhz ?50ns 14 boundary scan input valid to tck rising edge t bsdst 50 ? ns 15 tck rising edge to boundary scan input invalid t bsdht 50 ? ns 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 48 figure 21. jtag test clock input timing figure 22. jtag test access port timing 1 jtag timing specified at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 30 pf with dsc = 0b10, src = 0b00. these specifications apply to jtag boundary scan only. see ta b l e 3 4 for functional specifications. tck 1 2 3 3 2 tck 4 5 6 7 8 tms, tdi tdo electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 49 figure 23. jtag jcomp timing figure 24. jtag boundary scan timing tck jcomp 9 10 tck output signals input signals output signals 11 12 13 14 15 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 50 4.12.4 nexus timing table 34. nexus debug port timing 1 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 30 pf with dsc = 0b10. spec characteristic symbol min max unit 1 mcko cycle time t mcyc 2 2 2 the nexus aux port runs up to 82 mhz (pending characterization). set npc_pcr[mkco_div] to correct division depending on the system frequency, not to exceed maximum nexus aux port frequency. 8t cyc 3 3 see notes on t cyc ta b l e 2 7 in section section 4.11.1, clocking . 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 4 4 mdo, mseo , and evto data is held valid until next mcko low cycle. t mdov ?0.1 0.2 t mcyc 4 mcko low to mseo data valid 4 t mseov ?0.1 0.2 t mcyc 5 mcko low to evto data valid 4 t evtov ?0.1 0.2 t mcyc 6 evti pulse width t evtipw 4.0 ? t tcyc 3 7 evto pulse width t evtopw 1? t mcyc 8 tck cycle time t tcyc 4 5 5 lower frequency is required to be fully compliant to standard. ?t cyc 3 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8? ns 11 tdi, tms data hold time t ntdih, t ntmsh 5? ns 12 tck low to tdo data valid t ntdov 012.5 ns 13 rdy valid to mcko 6 6 the rdy pin timing is asynchronous to mcko. the timing is guaranteed by design to function correctly. ???? electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 51 figure 25. nexus timings 4 1 2 3 5 mcko mdo mseo evto output data valid 7 evti 6 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 52 figure 26. nexus tck, tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck 8 9 electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 53 4.12.5 external bus interface (ebi) timing table 35. bus operation timing 1 spec characteristic symbol 66 mhz (ext. bus freq) 2 3 unit notes min max 1 d_clkout period t c 15.2 ? ns signals are measured at 50% v dde . 2 d_clkout duty cycle t cdc 45% 55% t c 3 d_clkout rise time t crt ?? 4 ns 4 d_clkout fall time t cft ?? 4 ns 5 d_clkout posedge to output signal invalid or high z (hold time) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] t coh 1.0/1.5 ? ns hold time selectable via siu_eccr[ebts] bit: ebts = 0: 1.0 ns ebts = 1: 1.5 ns 6 d_clkout posedge to output signal valid (output delay) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] t cov ? 7.0/7.5 ns output valid time selectable via siu_eccr[ebts] bit: ebts = 0: 7.0 ns ebts = 1: 7.5 ns mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 54 figure 27. d_clkout timing 7 input signal valid to d_clkout posedge (setup time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts t cis 5.0/4.5 ? ns input setup time selectable via siu_eccr[ebts] bit: ebts = 0; 5.0ns ebts = 1; 4.5ns 8 d_clkout posedge to input signal invalid (hold time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts t cih 1.0 ? ns 9 d_ale pulse width t apw 6.5 ? ns the timing is for asynchronous external memory system. 10 d_ale negated to address invalid t aai 2.0/1.0 5 ? ns the timing is for asynchronous external memory system. ale is measured at 50% of vdde. 1 ebi timing specified at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2 speed is the nominal maximum frequency. max speed is the ma ximum speed allowed including frequency modulation (fm). 270 mhz parts allow for 264 mhz system clock + 2% fm. 3 depending on the internal bus speed, set t he siu_eccr[ebdf] bits correctly not to exceed maximum external bus frequency. the maximum external bus frequency is 66 mhz. 4 refer to fast pad timing in ta b l e 3 0 and table 31 . 5 ale hold time spec is temperature dependant. 1.0 n s spec applies for temperature range -40 to 0 ? c. 2.0 ns spec applies to temperatures > 0 ? c. this spec has no dependency on siu_eccr[ebts] bit. table 35. bus operation timing 1 (continued) spec characteristic symbol 66 mhz (ext. bus freq) 2 3 unit notes min max 1 2 2 3 4 d_clkout v dde / 2 v ol_f v oh_f electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 55 figure 28. synchronous output timing 6 5 5 d_clkout bus 5 output signal output v dde / 2 v dde / 2 v dde / 2 6 5 output signal v dde / 2 6 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 56 figure 29. synchronous input timing figure 30. ale signal timing 7 8 d_clkout input bus 7 8 input signal v dde / 2 v dde / 2 v dde / 2 ipg_clk d_clkout d_ale d_ts addr data d_add/d_dat 9 10 electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 57 4.12.6 external interrupt timing (irq pin) figure 31. external interrupt timing 4.12.7 etpu timing table 36. external interrupt timing 1 1 irq timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . spec characteristic symbol min max unit 1 irq pulse width low t ipwl 3?t cyc 2 2 see notes on t cyc on figure 16 and table 27 in section 4.11.1, clocking . 2 irq pulse width high t ipwh 3?t cyc 2 3 irq edge to edge time 3 3 applies when irq pins are configured for rising edge or falling edge events, but not both. t icyc 6?t cyc 2 table 37. etpu timing 1 1 etpu timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 200 pf with src = 0b00. spec characteristic symbol min max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 2 see notes on t cyc on figure 16 and ta b l e 2 7 in section 4.11.1, clocking . 2 etpu output channel pulse width t ocpw 1 3 3 this specification does not in clude the rise and fall times. when calculating the minimum etpu pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad configuration registers (pcr). ?t cyc 2 irq 1 2 3 mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 58 figure 32. etpu timing 4.12.8 emios timing table 38. emios timing 1 1 emios timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 50 pf with src = 0b00. spec characteristic symbol min max unit 1 emios input pulse width t mipw 4?t cyc 2 2 see notes on t cyc on figure 16 and ta b l e 2 7 in section 4.11.1, clocking . 2 emios output pulse width t mopw 1 3 3 this specification does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad configuration registers (pcr). ?t cyc 2 1 2 etpu output etpu input and tcrclk electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 59 figure 33. emios timing 4.12.9 dspi timing table 39. dspi timing 1 2 spec characteristic symbol peripheral bus freq: 132 mhz unit min max 1 dspi cycle time 3, 4 master (mtfe = 0) slave (mtfe = 0) master (mtfe = 1) slave (mtfe = 1) t sck t sys * 2 t sys *32768*7 ns 2 pcs to sck delay 5 t csc 12 ? ns 3 after sck delay 6 master mode slave mode t asc t sys * 2 t sys *3 ? constraints 7 ? ns 4 sck duty cycle t sdc 0.33 * t sck 0.66 * t sck ns 5 slave access time (ss active to sout valid) t a ? 25 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ns 7pcs x to pcss time t pcsc t sys * 2 t sys * 7 ns 8pcss to pcs x time t pasc t sys * 2 t sys * 7 ns 1 2 emios output emios input mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 60 the dspi in this device can be configured to serialize data to an external device th at implements the microsecond bus protocol. dspi pins support 5 v logic levels or low voltage differential signalling (lvds) for data and clock signals to improve high speed operation. 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 8 master (mtfe = 1, cpha = 1) t sui 20 4 6 20 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 8 master (mtfe = 1, cpha = 1) t hi ?3 7 12 ?3 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 5 25 13 5 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 2.5 3 ?5 ? ? ? ? ns ns ns ns 1 dspi timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, and t a =t l to t h 2 speed is the nominal maximum frequency of platform clock (f platf ). max speed is the maximum speed allowed including frequency modulation (fm). 270 mhz parts allow for 264 mhz for system core clock (f sys ) + 2% fm. 3 the minimum dspi cycle time restricts the baud rate selectio n for given system clock rate. these numbers are calculated based on two devices communicating over a dspi link. 4 the actual minimum sck cycle time is limited by pad performance. 5 the maximum value is pr ogrammable in dspi_ctar n [pssck] and dspi_ctar n [cssck]. 6 the maximum value is pr ogrammable in dspi_ctar n [pasc] and dspi_ctar n [asc]. 7 for example, external master should start sck clock no t earlier than 3 system clock periods after assertion ss 8 this number is calculated assuming the smpl _pt bitfield in dspi_mcr is set to 0b10. table 40. dspi lvds timing 1, 2 1 these are typical values that are estimated from simulation. 2 see dspi lvds pad related data in table 16 . characteristic symbol min max unit lvds clock to data/chip select outputs t lvdsdata ?0.25 t scyc +0.25 t scyc ns table 39. dspi timing 1 2 (continued) spec characteristic symbol peripheral bus freq: 132 mhz unit min max electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 61 figure 34. dspi classic spi timing ? master, cpha = 0 figure 35. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 62 figure 36. dspi classic spi timing ? slave, cpha = 0 figure 37. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) electrical characteristics mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 63 figure 38. dspi modified transfer format timing ? master, cpha = 0 figure 39. dspi modified transfer format timing ? master, cpha = 1 pcs x 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) pcs x 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) mpc5674f microcontroller data sheet, rev. 9 electrical characteristics freescale semiconductor 64 figure 40. dspi modified transfer format timing ? slave, cpha = 0 figure 41. dspi modified transfer format timing ? slave, cpha = 1 figure 42. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) pcs x 7 8 pcss package information mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 65 5 package information the latest package outline drawings are available on the product summary pages on our website: http://www.freescale.co m/powerarchitecture . the following table lists the package case number. use these numbers in the webpage?s keyword search engine to find the latest package outline drawings. table 41. package information package type case outline number 324 tepbga 98ass23840w 416 tepbga 98are10523d 516 tepbga 98ars10503d mpc5674f microcontroller data sheet, rev. 9 package information freescale semiconductor 66 5.1 324-pin package the package drawings of the 324-p in tepbga package are shown in figure 43 and figure 44 . figure 43. 324 tepbga package (1 of 2) package information mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 67 figure 44. 324 tepbga package (2 of 2) mpc5674f microcontroller data sheet, rev. 9 package information freescale semiconductor 68 5.2 416-pin package the package drawings of the 416-p in tepbga package are shown in figure 45 and figure 46 . figure 45. 416 tepbga package (1 of 2) package information mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 69 figure 46. 416 tepbga package (2 of 2) mpc5674f microcontroller data sheet, rev. 9 package information freescale semiconductor 70 5.3 516-pin package the package drawings of the 516-p in tepbga package are shown in figure 47 and figure 48 . figure 47. 516 tepbga package (1 of 2) package information mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 71 figure 48. 516 tepbga package (2 of 2) mpc5674f microcontroller data sheet, rev. 9 product documentation freescale semiconductor 72 6 product documentation this data sheet is labeled as a particular type: product previe w, advance information, or technical data. definitions of these types are available at: http://www.freescale.com. the following documents are required for a complete description of the device and are necessary to design properly with the parts: ? mpc5674f microprocessor reference manual (document number mpc5674frm). signal properties and muxing mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 73 appendix a signal properties and muxing the following table shows the signals properties for each pin on the mpc5674f. for each port pin that has an associated siu_pcr n register to control its pin propertie s, the supported functions column lists the functions associated with the programming of the siu_pcr n [pa] bit in the order: primary function (p), f unction 2 (f2), function 3 (f3), and gpio (g). see figure 49 . u figure 49. supported functions example primary functions secondary functions gpio functions are are listed first are alternate functions listed last gpio/ pcr 1 signal name 2 p/ f/ gfunction 3 function summary i/o pad type 113 tcrclka_irq7_gpio113 p tcrclka etpu a tcr clock i 5v m a1 irq7 external interrupt request i a2 ??? g gpio113 gpio i/o function not implemented on this device table 2. signal properties summary mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 74 table 42. signal properties and muxing summary gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 etpu_a 113 tcrclka_irq7_ gpio113 p tcrclka etpu a tcr clock i mh v ddeh1 ?/up ?/up k1 l1 k4 a1 irq7 external interrupt request i a2 ?? ? g gpio113 gpio i/o 114 etpua0_etpua12_ gpio114 p etpua0 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k2 l2 l6 a1 etpua12 etpu a channel (output only) o a2 ?? ? g gpio114 gpio i/o 115 etpua1_etpua13_ gpio115 p etpua1 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j1 l3 j1 a1 etpua13 etpu a channel (output only) o a2 ?? ? g gpio115 gpio i/o 116 etpua2_etpua14_ gpio116 p etpua2 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j2 l4 j2 a1 etpua14 etpu a channel (output only) o a2 ?? ? g gpio116 gpio i/o 117 etpua3_etpua15_ gpio117 p etpua3 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j3 k1 h4 a1 etpua15 etpu a channel (output only) o a2 ?? ? g gpio117 gpio i/o 118 etpua4_etpua16_ gpio118 p etpua4 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j4 k2 j4 a1 etpua16 etpu a channel (output only) o a2 ?? ? g gpio118 gpio i/o mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 75 119 etpua5_etpua17_ gpio119 p etpua5 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h1 k3 h1 a1 etpua17 etpu a channel (output only) o a2 ?? ? g gpio119 gpio i/o 120 etpua6_etpua18_ gpio120 p etpua6 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h2 k4 k5 a1 etpua18 etpu a channel (output only) o a2 ?? ? g gpio120 gpio i/o 121 etpua7_etpua19_ gpio121 p etpua7 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg ? j1 h2 a1 etpua19 etpu a channel (output only) o a2 ?? ? g gpio121 gpio i/o 122 etpua8_etpua20_ gpio122 p etpua8 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg ? j2 h3 a1 etpua20 etpu a channel (output only) o a2 ?? ? g gpio122 gpio i/o 123 etpua9_etpua21_ gpio123 p etpua9 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h3 j3 j3 a1 etpua21 etpu a channel (output only) o a2 ?? ? g gpio123 gpio i/o 124 etpua10_etpua22_ gpio124 p etpua10 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g1 j4 k6 a1 etpua22 etpu a channel (output only) o a2 ?? ? g gpio124 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 76 125 etpua11_etpua23_ gpio125 p etpua11 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g2 h1 g1 a1 etpua23 etpu a channel (output only) o a2 ?? ? g gpio125 gpio i/o 126 etpua12_pcsb1_ gpio126 p etpua12 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g3 h2 j5 a1 pcsb1 dspi b peripheral chip select o a2 ?? ? g gpio126 gpio i/o 127 etpua13_pcsb3_ gpio127 p etpua13 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f1 h4 g2 a1 pcsb3 dspi b peripheral chip select o a2 ?? ? g gpio127 gpio i/o 128 etpua14_pcsb4_ gpio128 p etpua14 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f2 h3 h5 a1 pcsb4 dspi b peripheral chip select o a2 ?? ? g gpio128 gpio i/o 129 etpua15_pcsb5_ gpio129 p etpua15 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f3 g1 g3 a1 pcsb5 dspi b peripheral chip select o a2 ?? ? g gpio129 gpio i/o 130 etpua16_pcsd1_ gpio130 p etpua16 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h4 g2 h6 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio130 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 77 131 etpua17_pcsd2_ gpio131 p etpua17 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g4 g3 g4 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio131 gpio i/o 132 etpua18_pcsd3_ gpio132 p etpua18 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg ? g4 g5 a1 pcsd3 dspi d peripheral chip select o a2 ?? ? g gpio132 gpio i/o 133 etpua19_pcsd4_ gpio133 p etpua19 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg ? f1 f1 a1 pcsd4 dspi d peripheral chip select o a2 ?? ? g gpio133 gpio i/o 134 etpua20_irq8_ gpio134 p etpua20 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e1 f2 f2 a1 irq8 external interrupt request i a2 ?? ? g gpio134 gpio i/o 135 etpua21_irq9_ gpio135 p etpua21 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg c1 f3 f3 a1 irq9 external interrupt request i a2 ?? ? g gpio135 gpio i/o 136 etpua22_irq10_ gpio136 p etpua22 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e2 f4 f4 a1 irq10 external interrupt request i a2 ?? ? g gpio136 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 78 137 etpua23_irq11_ gpio137 p etpua23 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d1 e1 e1 a1 irq11 external interrupt request i a2 ?? ? g gpio137 gpio i/o 138 etpua24_irq12_ gpio138 p etpua24 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e3 e2 e2 a1 irq12 external interrupt request i a2 ?? ? g gpio138 gpio i/o 139 etpua25_irq13_ gpio139 p etpua25 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d2 e3 e3 a1 irq13 external interrupt request i a2 ?? ? g gpio139 gpio i/o 140 etpua26_irq14_ gpio140 p etpua26 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg c2 e4 e4 a1 irq14 external interrupt request i a2 ?? ? g gpio140 gpio i/o 141 etpua27_irq15_ gpio141 p etpua27 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f4 d1 d1 a1 irq15 external interrupt request i a2 ?? ? g gpio141 gpio i/o 142 etpua28_pcsc1_ gpio142 p etpua28 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg ? d2 d2 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio142 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 79 143 etpua29_pcsc2_ gpio143 p etpua29 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg ? d3 d3 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio143 gpio i/o 144 etpua30_pcsc3_ gpio144 p etpua30 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e4 c1 c1 a1 pcsc3 dspi c peripheral chip select o a2 ?? ? g gpio144 gpio i/o 145 etpua31_pcsc4_ gpio145 p etpua31 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d3 c2 c2 a1 pcsc4 dspi c peripheral chip select o a2 ?? ? g gpio145 gpio i/o etpu_b 146 tcrclkb_irq6_ gpio146 p tcrclkb etpu b tcr clock i mh v ddeh6 ?/up ?/up p19 t23 v25 a1 irq6 external interrupt request i a2 ?? ? g gpio146 gpio i/o 147 etpub0_etpub16_ gpio147 p etpub0 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n19 t24 v26 a1 etpub16 etpu b channel (output only) o a2 ?? ? g gpio147 gpio i/o 148 etpub1_etpub17_ gpio148 p etpub1 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r19 t25 u22 a1 etpub17 etpu b channel (output only) o a2 ?? ? g gpio148 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 80 149 etpub2_etpub18_ gpio149 p etpub2 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r22 t26 u23 a1 etpub18 etpu b channel (output only) o a2 ?? ? g gpio149 gpio i/o 150 etpub3_etpub19_ gpio150 p etpub3 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r21 r23 t22 a1 etpub19 etpu b channel (output only) o a2 ?? ? g gpio150 gpio i/o 151 etpub4_etpub20_ gpio151 p etpub4 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p22 r24 u24 a1 etpub20 etpu b channel (output only) o a2 ?? ? g gpio151 gpio i/o 152 etpub5_etpub21_ gpio152 p etpub5 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p21 r25 u25 a1 etpub21 etpu b channel (output only) o a2 ?? ? g gpio152 gpio i/o 153 etpub6_etpub22_ gpio153 p etpub6 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n22 r26 u26 a1 etpub22 etpu b channel (output only) o a2 ?? ? g gpio153 gpio i/o 154 etpub7_etpub23_ gpio154 p etpub7 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m19 p23 t23 a1 etpub23 etpu b channel (output only) o a2 ?? ? g gpio154 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 81 155 etpub8_etpub24_ gpio155 p etpub8 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n21 p24 t24 a1 etpub24 etpu b channel (output only) o a2 ?? ? g gpio155 gpio i/o 156 etpub9_etpub25_ gpio156 p etpub9 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m22 p25 r22 a1 etpub25 etpu b channel (output only) o a2 ?? ? g gpio156 gpio i/o 157 etpub10_etpub26_ gpio157 p etpub10 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m20 p26 t25 a1 etpub26 etpu b channel (output only) o a2 ?? ? g gpio157 gpio i/o 158 etpub11_etpub27_ gpio158 p etpub11 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m21 n24 t26 a1 etpub27 etpu b channel (output only) o a2 ?? ? g gpio158 gpio i/o 159 etpub12_etpub28_ gpio159 p etpub12 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg l19 n25 r23 a1 etpub28 etpu b channel (output only) o a2 ?? ? g gpio159 gpio i/o 160 etpub13_etpub29_ gpio160 p etpub13 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg l20 n26 p22 a1 etpub29 etpu b channel (output only) o a2 ?? ? g gpio160 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 82 161 etpub14_etpub30_ gpio161 p etpub14 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg l21 m25 r24 a1 etpub30 etpu b channel (output only) o a2 ?? ? g gpio161 gpio i/o 162 etpub15_etpub31_ gpio162 p etpub15 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? m24 r25 a1 etpub31 etpu b channel (output only) o a2 ?? ? g gpio162 gpio i/o 163 etpub16_pcsa1_ gpio163 p etpub16 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p20 u26 v24 a1 pcsa1 dspi a peripheral chip select o a2 ?? ? g gpio163 gpio i/o 164 etpub17_pcsa2_ gpio164 p etpub17 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r20 u25 t21 a1 pcsa2 dspi a peripheral chip select o a2 ?? ? g gpio164 gpio i/o 165 etpub18_pcsa3_ gpio165 p etpub18 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t20 u24 w26 a1 pcsa3 dspi a peripheral chip select o a2 ?? ? g gpio165 gpio i/o 166 etpub19_pcsa4_ gpio166 p etpub19 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t19 u23 w25 a1 pcsa4 dspi a peripheral chip select o a2 ?? ? g gpio166 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 83 167 etpub20_ gpio167 p etpub20 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? v26 w24 a1 ?? ? a2 ?? ? g gpio167 gpio i/o 168 etpub21_ gpio168 p etpub21 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? v25 v22 a1 ?? ? a2 ?? ? g gpio168 gpio i/o 169 etpub22_ gpio169 p etpub22 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? v24 v23 a1 ?? ? a2 ?? ? g gpio169 gpio i/o 170 etpub23_ gpio170 p etpub23 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? w26 u21 a1 ?? ? a2 ?? ? g gpio170 gpio i/o 171 etpub24_ gpio171 p etpub24 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? w25 y25 a1 ?? ? a2 ?? ? g gpio171 gpio i/o 172 etpub25_ gpio172 p etpub25 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? w24 w21 a1 ?? ? a2 ?? ? g gpio172 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 84 173 etpub26_ gpio173 p etpub26 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? v23 y23 a1 ?? ? a2 ?? ? g gpio173 gpio i/o 174 etpub27_ gpio174 p etpub27 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? y25 y24 a1 ?? ? a2 ?? ? g gpio174 gpio i/o 175 etpub28_ gpio175 p etpub28 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? y24 aa24 a1 ?? ? a2 ?? ? g gpio175 gpio i/o 176 etpub29_ gpio176 p etpub29 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ? y23 w22 a1 ?? ? a2 ?? ? g gpio176 gpio i/o 177 etpub30_ gpio177 p etpub30 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u20 aa24 ab24 a1 ?? ? a2 ?? ? g gpio177 gpio i/o 178 etpub31_ gpio178 p etpub31 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u19 ab24 y22 a1 ?? ? a2 ?? ? g gpio178 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 85 gpio, irq, flexray 440 tcrclkc _ gpio440 9 p ?? ?mhv ddeh7 ?/up ?/up b22 b26 f22 a1 ?? ? a2 ?? ? g gpio440 gpio i/o 441 etpuc0 _ gpio441 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg c21 c25 c25 a1 ?? ? a2 ?? ? g gpio441 gpio i/o 442 etpuc1 _ gpio442 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d20 c26 c26 a1 ?? ? a2 ?? ? g gpio442 gpio i/o 443 etpuc2 _ gpio443 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d22 d25 d25 a1 ?? ? a2 ?? ? g gpio443 gpio i/o 444 etpuc3 _ gpio444 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d21 d26 d26 a1 ?? ? a2 ?? ? g gpio444 gpio i/o 445 etpuc4 _ gpio445 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg e22 e24 e24 a1 ?? ? a2 ?? ? g gpio445 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 86 446 etpuc5 _ gpio446 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg e19 e25 e25 a1 ?? ? a2 ?? ? g gpio446 gpio i/o 447 etpuc6 _ gpio447 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg ? e26 e26 a1 ?? ? a2 ?? ? g gpio447 gpio i/o 448 etpuc7 _ gpio448 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg ? f23 f23 a1 ?? ? a2 ?? ? g gpio448 gpio i/o 449 etpuc8 _ gpio449 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg ? f24 f24 a1 ? ? ? a2 ?? ? g gpio449 gpio i/o 450 etpuc9_ irq0_ gpio450 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f22 f25 f25 a1 irq0 external interrupt request i a2 ?? ? g gpio450 gpio i/o 451 etpuc10_ _irq1_ gpio451 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg e20 f26 f26 a1 irq1 external interrupt request i a2 ?? ? g gpio451 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 87 452 etpuc11_ irq2_ gpio452 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg e21 g23 g22 a1 irq2 external interrupt request i a2 ?? ? g gpio452 gpio i/o 453 etpuc12_ irq3_ gpio453 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f19 g24 g23 a1 irq3 external interrupt request i a2 ?? ? g gpio453 gpio i/o 454 etpuc13_ 3_irq4_ gpio454 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f21 g25 g24 a1 irq4 external interrupt request i a2 ?? ? g gpio454 gpio i/o 455 etpuc14_ 4_irq5_ gpio455 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f20 g26 g25 a1 irq5 external interrupt request i a2 ?? ? g gpio455 gpio i/o 456 etpuc15_ _ gpio456 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg ? h23 g26 a1 ?? ? a2 ?? ? g gpio456 gpio i/o 457 etpuc16_ fr_a_tx_ gpio457 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg ? h24 h22 a1 fr_a_tx flexray a transfer o a2 ?? ? g gpio457 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 88 458 etpuc17_ fr_a_rx_ gpio458 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g22 h25 h23 a1 fr_a_rx flexray a receive i a2 ?? ? g gpio458 gpio i/o 459 etpuc18_ fr_a_tx_en_ gpio459 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g20 h26 h24 a1 fr_a_tx_en flexray a transfer enable o a2 ?? ? g gpio459 gpio i/o 460 etpuc19_ txda_ gpio460 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g21 j23 h21 a1 txda esci a transmit o a2 ?? ? g gpio460 gpio i/o 461 etpuc20_ rxda _ gpio461 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g19 j24 h25 a1 rxda esci a receive i a2 ?? ? g gpio461 gpio i/o 462 etpuc21_ txdb_ gpio462 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h22 j25 h26 a1 txdb esci b transmit o a2 ?? ? g gpio462 gpio i/o 463 etpuc22_ rxdb_ gpio463 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h21 j26 j22 a1 rxdb esci b receive i a2 ?? ? g gpio463 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 89 464 etpuc23_ pcsd5_ gpio464 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h20 k23 j23 a1 pcsd5 dspi d peripheral chip select o a2 maa0 adc a mux address 0 o a3 mab0 adc b mux address 0 o g gpio464 gpio i/o 465 etpuc24_ pcsd4_ gpio465 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j22 k24 j24 a1 pcsd4 dspi d peripheral chip select o a2 maa1 adc a mux address 1 o a4 mab1 adc b mux address 1 o g gpio465 gpio i/o 466 etpuc25_ pcsd3_ gpio466 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k22 k25 k21 a1 pcsd3 dspi d peripheral chip select o a2 maa2 adc a mux address 2 o a3 mab2 adc b mux address 2 o g gpio466 gpio i/o 467 etpuc26_ pcsd2_ gpio467 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j21 k26 j25 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio467 gpio i/o 468 etpuc27_ pcsd1_ gpio468 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j19 l23 j26 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio468 gpio i/o 469 etpuc28_ pcsd0_ gpio469 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j20 l24 k22 a1 pcsd0 dspi d peripheral chip select i/o a2 ?? ? g gpio469 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 90 470 etpuc29_ sckd_ gpio470 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k21 l25 k23 a1 sckd dspi d clock i/o a2 ?? ? g gpio470 gpio i/o 471 etpuc30_ soutd_ gpio471 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k20 l26 k24 a1 soutd dspi d data output o a2 ?? ? g gpio471 gpio i/o 472 etpuc31_ sind_ gpio472 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k19 m23 k25 a1 sind dspi d data input i a2 ?? ? g gpio472 gpio i/o emios 179 emios0_etpua0_ gpio179 p emios0 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa9 ae10 ac13 a1 etpua0 etpu a channel o a2 ?? ? g gpio179 gpio i/o 180 emios1_etpua1_ gpio180 p emios1 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab9 af10 ab13 a1 etpua1 etpu a channel o a2 ?? ? g gpio180 gpio i/o 181 emios2_etpua2_ gpio181 p emios2 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg y10 ad11 ad13 a1 etpua2 etpu a channel o a2 ?? ? g gpio181 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 91 182 emios3_etpua3_ gpio182 p emios3 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa10 ae11 ae13 a1 etpua3 etpu a channel o a2 ?? ? g gpio182 gpio i/o 183 emios4_etpua4_ gpio183 p emios4 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab10 af11 af13 a1 etpua4 etpu a channel o a2 ?? ? g gpio183 gpio i/o 184 emios5_etpua5_ gpio184 p emios5 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg y11 ad12 af14 a1 etpua5 etpu a channel o a2 ?? ? g gpio184 gpio i/o 185 emios6_etpua6_ gpio185 p emios6 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ? ae12 ae14 a1 etpua6 etpu a channel o a2 ?? ? g gpio185 gpio i/o 186 emios7_etpua7_ gpio186 p emios7 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab11 af12 ad14 a1 etpua7 etpu a channel o a2 ?? ? g gpio186 gpio i/o 187 emios8_etpua8_ gpio187 p emios8 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg w10 ac13 ac14 a1 etpua8 etpu a channel o a2 ?? ? g gpio187 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 92 188 emios9_etpua9_ gpio188 p emios9 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg w11 ad13 af15 a1 etpua9 etpu a channel o a2 ?? ? g gpio188 gpio i/o 189 emios10_sckd_ gpio189 p emios10 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa11 ae13 ae15 a1 sckd dspi d clock o a2 ?? ? g gpio189 gpio i/o 190 emios11_sind_ gpio190 p emios11 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab12 af13 ab14 a1 sind dspi d data input i a2 ?? ? g gpio190 gpio i/o 191 emios12_soutc_ gpio191 p emios12 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab13 af14 ad15 a1 soutc dspi c data output o a2 ?? ? g gpio191 gpio i/o 192 emios13_soutd_ gpio192 p emios13 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa12 ae14 ac15 a1 soutd dspi d data output o a2 ?? ? g gpio192 gpio i/o 193 emios14_irq0_ gpio193 p emios14 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg y12 ac14 af17 a1 irq0 external interrupt request i a2 cntxd flexcan d transmit o g gpio193 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 93 194 emios15_irq1_ gpio194 p emios15 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg y13 ad14 ae16 a1 irq1 external interrupt request i a2 cnrxd flexcan d receive i g gpio194 gpio i/o 195 emios16_etpub0_ gpio195 p emios16 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab14 af15 ad16 a1 etpub0 etpu b channel o a2 fr_dbg[3] flexray debug o g gpio195 gpio i/o 196 emios17_etpub1_ gpio196 p emios17 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa13 ae15 ab15 a1 etpub1 etpu b channel o a2 fr_dbg[2] flexray debug o g gpio196 gpio i/o 197 emios18_etpub2_ gpio197 p emios18 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg w12 ac15 ad17 a1 etpub2 etpu b channel o a2 fr_dbg[1] flexray debug o g gpio197 gpio i/o 198 emios19_etpub3_ gpio198 p emios19 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg y14 ad15 ab16 a1 etpub3 etpu b channel o a2 fr_dbg[0] flexray debug o g gpio198 gpio i/o 199 emios20_etpub4_ gpio199 p emios20 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab15 af16 af16 a1 etpub4 etpu b channel o a2 ?? ? g gpio199 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 94 200 emios21_etpub5_ gpio200 p emios21 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa14 ae16 ae17 a1 etpub5 etpu b channel o a2 ?? ? g gpio200 gpio i/o 201 emios22_etpub6_ gpio201 p emios22 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg w13 ac16 ac16 a1 etpub6 etpu b channel o a2 ?? ? g gpio201 gpio i/o 202 emios23_etpub7_ gpio202 p emios23 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg y15 ad16 aa16 a1 etpub7 etpu b channel o a2 ?? ? g gpio202 gpio i/o 203 emios24_pcsb0_ gpio203 p emios24 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ab16 af17 ac17 a1 pcsb0 dspi b peripheral chip select i/o a2 ?? ? g gpio203 gpio i/o 204 emios25_pcsb1_ gpio204 p emios25 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa15 ae17 af18 a1 pcsb1 dspi b peripheral chip select o a2 ?? ? g gpio204 gpio i/o 432 emios26_pcsb2_ gpio432 p emios26 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg y16 ad17 ae18 a1 pcsb2 dspi b peripheral chip select o a2 ?? ? g gpio432 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 95 433 emios27_pcsb3_ gpio433 p emios27 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg w14 ac17 ad18 a1 pcsb3 dspi b peripheral chip select o a2 ?? ? g gpio433 gpio i/o 434 emios28_pcsc0_ gpio434 p emios28 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa16 af18 ac18 a1 pcsc0 dspi c peripheral chip select i/o a2 ?? ? g gpio434 gpio i/o 435 emios29_pcsc1_ gpio435 p emios29 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg aa17 ae18 ab17 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio435 gpio i/o 436 emios30_pcsc2_ gpio436 p emios30 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg y17 ad18 af19 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio436 gpio i/o 437 emios31_pcsc5_ gpio437 p emios31 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg w15 ac18 aa17 a1 pcsc5 dspi c peripheral chip select o a2 ?? ? g gpio437 gpio i/o eqadc ?ana0 p ana0 10 eqadc a analog input i ae/up- down v dda_a1 ana0 ana0 a4 a4 a4 ?ana1 p ana1 10 eqadc a analog input i ae/up- down v dda_a1 ana1 ana1 a5 b5 b5 ?ana2 p ana2 10 eqadc a analog input i ae/up- down v dda_a1 ana2 ana2 b5 c5 c5 table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 96 ?ana3 p ana3 10 eqadc a analog input i ae/up- down v dda_a1 ana3 ana3 b6 d6 d6 ?ana4 p ana4 10 eqadc a analog input i ae/up- down v dda_a1 ana4 ana4 a6 a5 a5 ?ana5 p ana5 10 eqadc a analog input i ae/up- down v dda_a1 ana5 ana5 a7 b6 b6 ?ana6 p ana6 10 eqadc a analog input i ae/up- down v dda_a1 ana6 ana6 b7 c6 c6 ?ana7 p ana7 10 eqadc a analog input i ae/up- down v dda_a1 ana7 ana7 b8 d7 c7 ?ana8 p ana8 eqadc a analog input i ae v dda_a1 ana8 ana8 c5 a6 d7 ?ana9 p ana9 eqadc a analog input i ae v dda_a1 ana9 ana9 c7 c7 a6 ?ana10 p ana10 eqadc a analog input i ae v dda_a1 ana10 ana10 c6 b7 b7 ?ana11 p ana11 eqadc a analog input i ae v dda_a1 ana11 ana11 d6 a7 a7 ?ana12 p ana12 eqadc a analog input i ae v dda_a1 ana12 ana12 d7 d8 d8 ?ana13 p ana13 eqadc a analog input i ae v dda_a1 ana13 ana13 c8 c8 c8 ?ana14 p ana14 eqadc a analog input i ae v dda_a1 ana14 ana14 d8 b8 b8 ?ana15 p ana15 eqadc a analog input i ae v dda_a1 ana15 ana15 a8 a8 a8 ?ana16 p ana16 eqadc a analog input i ae v dda_a1 ana16 ana16 d9 d9 d9 ?ana17 p ana17 eqadc a analog input i ae v dda_a1 ana17 ana17 c9 c9 c9 ?ana18 p ana18 eqadc a analog input i ae v dda_a1 ana18 ana18 d10 d10 d10 ?ana19 p ana19 eqadc a analog input i ae v dda_a1 ana19 ana19 c10 c10 c10 ?ana20 p ana20 eqadc a analog input i ae v dda_a1 ana20 ana20 d11 d11 d11 ?ana21 p ana21 eqadc a analog input i ae v dda_a1 ana21 ana21 c11 c11 c11 ?ana22 p ana22 eqadc a analog input i ae v dda_a1 ana22 ana22 d12 d12 c12 ?ana23 p ana23 eqadc a analog input i ae v dda_a1 ana23 ana23 c12 c12 d12 ?an24 p an24 eqadc a and b shared analog input i ae v dda_a0 an24 an24 ? b12 b12 ?an25 p an25 eqadc a and b shared analog input i ae v dda_a0 an25 an25 ? d13 c13 ?an26 p an26 eqadc a and b shared analog input i ae v dda_a0 an26 an26 ? c13 d13 table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 97 ?an27 p an27 eqadc a and b shared analog input i ae v dda_a0 an27 an27 ? b13 b13 ?an28 p an28 eqadc a and b shared analog input i ae v dda_a0 an28 an28 ? a13 a13 ?an29 p an29 eqadc a and b shared analog input i ae v dda_a0 an29 an29 ? b14 a14 ?an30 p an30 eqadc a and b shared analog input i ae v dda_b1 an30 an30 ? c14 b14 ?an31 p an31 eqadc a and b shared analog input i ae v dda_b1 an31 an31 ? d14 c14 ?an32 p an32 eqadc a and b shared analog input i ae v dda_b1 an32 an32 ? a14 b15 ?an33 p an33 eqadc a and b shared analog input i ae v dda_b0 an33 an33 ? b15 d14 ?an34 p an34 eqadc a and b shared analog input i ae v dda_b0 an34 an34 ? c15 c15 ?an35 p an35 eqadc a and b shared analog input i ae v dda_b0 an35 an35 ? d15 d15 ?an36 p an36 eqadc a and b shared analog input i ae v dda_b1 an36 an36 ? a15 a15 ?an37 p an37 eqadc a and b shared analog input i ae v dda_b0 an37 an37 ? c16 c17 ?an38 p an38 eqadc a and b shared analog input i ae v dda_b0 an38 an38 ? c17 d16 ?an39 p an39 eqadc a and b shared analog input i ae v dda_b0 an39 an39 ? d16 c16 ?anb0 p anb0 eqadc b analog input i ae/up- down v dda_b0 anb0 anb0 b15 c18 c18 ?anb1 p anb1 eqadc b analog input i ae/up- down v dda_b0 anb1 anb1 b16 d17 d17 ?anb2 p anb2 eqadc b analog input i ae/up- down v dda_b0 anb2 anb2 a17 d18 d18 ?anb3 p anb3 eqadc b analog input i ae/up- down v dda_b0 anb3 anb3 a18 d19 d19 ?anb4 p anb4 eqadc b analog input i ae/up- down v dda_b0 anb4 anb4 b17 c19 b19 ?anb5 p anb5 eqadc b analog input i ae/up- down v dda_b0 anb5 anb5 b18 c20 a20 ?anb6 p anb6 eqadc b analog input i ae/up- down v dda_b0 anb6 anb6 a19 b19 c20 ?anb7 p anb7 eqadc b analog input i ae/up- down v dda_b0 anb7 anb7 a20 a20 c19 ?anb8 p anb8 eqadc b analog input i ae v dda_b0 anb8 anb8 d13 b20 b20 table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 98 ?anb9 p anb9 eqadc b analog input i ae v dda_b0 anb9 anb9 c14 d20 a21 ?anb10 p anb10 eqadc b analog input i ae v dda_b0 anb10 anb10 c13 b21 b21 ?anb11 p anb11 eqadc b analog input i ae v dda_b0 anb11 anb11 c15 a21 c21 ?anb12 p anb12 eqadc b analog input i ae v dda_b0 anb12 anb12 c16 c21 a22 ?anb13 p anb13 eqadc b analog input i ae v dda_b0 anb13 anb13 d14 d21 b22 ?anb14 p anb14 eqadc b analog input i ae v dda_b0 anb14 anb14 c17 a22 d20 ?anb15 p anb15 eqadc b analog input i ae v dda_b0 anb15 anb15 d15 b22 c22 ?anb16 p anb16 eqadc b analog input i ae v dda_b0 anb16 anb16 c18 c22 d21 ?anb17 p anb17 eqadc b analog input i ae v dda_b0 anb17 anb17 d16 a23 d22 ?anb18 p anb18 eqadc b analog input i ae v dda_b0 anb18 anb18 d17 b23 a23 ?anb19 p anb19 eqadc b analog input i ae v dda_b0 anb19 anb19 b19 c23 b23 ?anb20 p anb20 eqadc b analog input i ae v dda_b0 anb20 anb20 c19 d22 c23 ?anb21 p anb21 eqadc b analog input i ae v dda_b0 anb21 anb21 d18 a24 a24 ?anb22 p anb22 eqadc b analog input i ae v dda_b0 anb22 anb22 a21 b24 b24 ?anb23 p anb23 eqadc b analog input i ae v dda_b0 anb23 anb23 b20 a25 e20 ? vrh_a p vrh_a adc a voltage reference high i vddint v rh_a vrh_a vrh_a a10 a12 a12 ? vrl_a p vrl_a adc a voltage reference low i vssint v rl_a vrl_a vrl_a a11 a11 a11 ? vrh_b p vrh_b adc b voltage reference high i vddint v rh_b vrh_b vrh_b a16 a19 a19 ? vrl_b p vrl_b adc b voltage reference low i vssint v rl_b vrl_b vrl_b a15 a18 a18 ? refbypcb p refbypcb adc b reference bypass capacitor i ae v dda_b0 refbypcb refbypcb b12 b18 b18 ? refbypca p refbypca adc a reference bypass capacitor i ae v dda_a1 refbypca refbypca b11 b11 b11 ? vdda_a0 p vdda_a internal logi c supply input i vdde v dda_a0 vdda_a0 vdda_a0 a9 a9 a9 ? vdda_a1 p vdda_a internal logi c supply input i vdde v dda_a1 vdda_a1 vdda_a1 b9 b9 b9 ? refbypca1 p refbypca1 adc a reference bypass capacitor i ae v dda_a1 refbypca1 refbypca1 a12 a10 a10 ? vssa_a1 p vssa_a ground i vsse v ssa_a1 vssa_a1 vssa_a1 b10 b10 b10 ? vdda_b0 p vdda_b internal logi c supply input i vdde v dda_b0 vdda_b0 vdda_b0 a13 a16 a16 ? vdda_b1 p vdda_b internal logi c supply input i vdde v dda_b1 vdda_b1 vdda_b1 b13 b16 b16 table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 99 ? vssa_b0 p vssa_b ground i vsse v ssa_b0 vssa_b0 vssa_b0 b14 b17 b17 ? refbypcb1 p refbypcb1 adc b reference bypass capacitor i ae v dda_b0 refbypcb1 refbypcb1 a14 a17 a17 flexray 248 fr_a_tx_ gpio248 p fr_a_tx flexray a transfer o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) y5 ad4 ad4 a1 ?? ? a2 ?? ? g gpio248 gpio i/o 249 fr_a_rx_ gpio249 p fr_a_rx flexray a receive i fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) aa4 ae3 ae3 a1 ?? ? a2 ?? ? g gpio249 gpio i/o 250 fr_a_tx_en_ gpio250 p fr_a_tx_en flexray a transfer enable o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ab3 af3 af3 a1 ?? ? a2 ?? ? g gpio250 gpio i/o 251 fr_b_tx_ gpio251 p fr_b_tx flexray b transfer o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) y6 ad5 ad5 a1 ?? ? a2 ?? ? g gpio251 gpio i/o 252 fr_b_rx_ gpio252 p fr_b_rx flexray b receive i fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) aa5 ae4 ae4 a1 ?? ? a2 ?? ? g gpio252 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 100 253 fr_b_tx_en_ gpio253 p fr_b_tx_en flexray b transfer enable o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ab5 af4 af4 a1 ?? ? a2 ?? ? g gpio253 gpio i/o flexcan 83 cntxa_txda_ gpio83 p cntxa flexcan a transmit o mh v ddeh4 ?/up ?/up ab17 af19 ae19 a1 txda esci a transmit o a2 ?? ? g gpio83 gpio i/o 84 cnrxa_rxda_ gpio84 p cnrxa flexcan a receive i mh v ddeh4 ?/up ?/up aa18 ae19 ad19 a1 rxda esci a receive i a2 ?? ? g gpio84 gpio i/o 85 cntxb_pcsc3_ gpio85 p cntxb flexcan b transmit o mh v ddeh4 ?/up ?/up y18 ad19 ac19 a1 pcsc3 dspi c peripheral chip select o a2 ?? ? g gpio85 gpio i/o 86 cnrxb_pcsc4_ gpio86 p cnrxb flexcan b receive i mh v ddeh4 ?/up ?/up w18 ac19 aa19 a1 pcsc4 dspi c peripheral chip select o a2 ?? ? g gpio86 gpio i/o 87 cntxc_pcsd3_ gpio87 p cntxc flexcan c transmit o mh v ddeh4 ?/up ?/up w16 af20 af20 a1 pcsd3 dspi d peripheral chip select o a2 ?? ? g gpio87 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 101 88 cnrxc_pcsd4_ gpio88 p cnrxc flexcan c receive i mh v ddeh4 ?/up ?/up w17 ae20 ae20 a1 pcsd4 dspi d peripheral chip select o a2 ?? ? g gpio88 gpio i/o 246 cntxd_ gpio246 p cntxd flexcan d transmit o mh v ddeh4 ?/up ?/up ab21 ad20 ad20 a1 ?? ? a2 ?? ? g gpio246 gpio i/o 247 cnrxd_ gpio247 p cnrxd flexcan d receive i mh v ddeh4 ?/up ?/up y19 ac20 ac20 a1 ?? ? a2 ?? ? g gpio247 gpio i/o esci 89 txda_ gpio89 p txda esci a transmit o mh v ddeh1 ?/up ?/up ? m2 k2 a1 ?? ? a2 ?? ? g gpio89 gpio i/o 90 rxda _ gpio90 p rxda esci a receive i mh v ddeh1 ?/up ?/up ? m3 k3 a1 ?? ? a2 ?? ? g gpio90 gpio i 91 txdb_pcsd1_ gpio91 p txdb esci b transmit o mh v ddeh1 ?/up ?/up ? p1 k1 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio91 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 102 92 rxdb_pcsd5_ gpio92 p rxdb esci b receive i mh v ddeh1 ?/up ?/up ? n1 l5 a1 pcsd5 dspi d peripheral chip select o a2 ?? ? g gpio92 gpio i/o 244 txdc_etrig0_ gpio244 p txdc esci c transmit o mh v ddeh4 ?/up ?/up ? af23 af23 a1 etrig0 eqadc trigger input i a2 ?? ? g gpio244 gpio i/o 245 rxdc_ gpio245 p rxdc esci c receive i mh v ddeh5 ?/up ?/up ? ad22 ad22 a1 ?? ? a2 ?? ? g gpio245 gpio i/o dspi 93 scka_pcsc1_ gpio93 p scka dspi a clock i/o mh v ddeh3 ?/up ?/up y7 ad8 ab8 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio93 gpio i/o 94 sina_pcsc2_ gpio94 p sina dspi a data input i mh v ddeh3 ?/up ?/up aa7 af7 ae7 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio94 gpio i/o 95 souta_pcsc5_ gpio95 p souta dspi a data output o mh v ddeh3 ?/up ?/up ab7 ad7 ac7 a1 pcsc5 dspi c peripheral chip select o a2 ?? ? g gpio95 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 103 96 pcsa0_pcsd2_ gpio96 p pcsa0 dspi a peripheral chip select i/o mh v ddeh3 ?/up ?/up ab6 ae6 ad6 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio96 gpio i/o 97 pcsa1_ gpio97 p pcsa1 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ? ac6 ac6 a1 ?? ? a2 ?? ? g gpio97 gpio i/o 98 pcsa2_ gpio98 p pcsa2 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ? ac7 af6 a1 ?? ? a2 ?? ? g gpio98 gpio i/o 99 pcsa3_ gpio99 p pcsa3 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ? ae7 ad7 a1 ?? ? a2 ?? ? g gpio99 gpio i/o 100 pcsa4_ gpio100 p pcsa4 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ? ae5 ae5 a1 ?? ? a2 ?? ? g gpio100 gpio i/o 101 pcsa5_etrig1_ gpio101 p pcsa5 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up aa6 ad6 aa8 a1 etrig1 eqadc trigger input i a2 ?? ? g gpio101 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 104 102 sckb_ gpio102 p sckb dspi b clock i/o mh v ddeh3 ?/up ?/up y8 ae8 ac8 a1 ?? ? a2 ?? ? g gpio102 gpio i/o 103 sinb_ gpio103 p sinb dspi b data input i mh v ddeh3 ?/up ?/up aa8 ae9 ab9 a1 ?? ? a2 ?? ? g gpio103 gpio i/o 104 soutb_ gpio104 p soutb dspi b data output o mh v ddeh3 ?/up ?/up ab8 af9 aa10 a1 ?? ? a2 ?? ? g gpio104 gpio i/o 105 pcsb0_pcsd2_ gpio105 p pcsb0 dspi b peripheral chip select i/o mh v ddeh3 ?/up ?/up y9 ad9 af8 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio105 gpio i/o 106 pcsb1_pcsd0_ gpio106 p pcsb1 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ? ac9 ae8 a1 pcsd0 dspi d peripheral chip select i/o a2 ?? ? g gpio106 gpio i/o 107 pcsb2_soutc_ gpio107 p pcsb2 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up w7 af8 ad8 a1 soutc dspi c data output o a2 ?? ? g gpio107 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 105 108 pcsb3_sinc_ gpio108 p pcsb3 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ? ad10 ac9 a1 sinc dspi c data input i a2 ?? ? g gpio108 gpio i/o 109 pcsb4_sckc_ gpio109 p pcsb4 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ? ac8 af7 a1 sckc dspi c clock i/o a2 ?? ? g gpio109 gpio i/o 110 pcsb5_pcsc0_ gpio110 p pcsb5 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ? af6 ae6 a1 pcsc0 dspi c peripheral chip select i/o a2 ?? ? g gpio110 gpio i/o 235 sckc_sck_c_lvdsp_ gpio235 p sckc dspi c clock i/o mh+ lvds v ddeh4 ?/up ?/up aa19 ad21 ad21 a1 sck_c_lvdsp lvds+ downstream signal positive output clock o a2 ?? ? g gpio235 gpio i/o 236 sinc_sck_c_lvdsm_ gpio236 p sinc dspi c data input i mh+ lvds v ddeh4 ?/up ?/up aa20 ae22 ae22 a1 sck_c_lvdsm lvds? downstream signal negative output clock o a2 ?? ? g gpio236 gpio i/o 237 soutc_sout_c_lvdsp_ gpio237 p soutc dspi c data output o mh+ lvds v ddeh4 ?/up ?/up ab18 af21 af21 a1 sout_c_lvdsp lvds+ downstream signal positive output data o a2 ?? ? g gpio237 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 106 238 pcsc0_sout_c_lvdsm_ gpio238 p pcsc0 dspi c peripheral chip select i/o mh+ lvds v ddeh4 ?/up ?/up ab19 ae21 ae21 a1 sout_c_lvdsm lvds? downstream signal negative output data o a2 ?? ? g gpio238 gpio i/o 239 pcsc1_ gpio239 p pcsc1 dspi c peripheral chip select o mh v ddeh4 ?/up ?/up ? ac22 ac22 a1 ?? ? a2 ?? ? g gpio239 gpio i/o 240 pcsc2_gpio240 p pcsc2 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ? ae23 ae23 a1 ?? ? a2 ?? ? g gpio240 gpio i/o 241 pcsc3_gpio241 p pcsc3 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ? ad23 ad23 a1 ?? ? a2 ?? ? g gpio241 gpio i/o 242 pcsc4_gpio242 p pcsc4 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ? af24 af24 a1 ?? ? a2 ?? ? g gpio242 gpio i/o 243 pcsc5_gpio243 p pcsc5 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ? ae24 ae24 a1 ?? ? a2 ?? ? g gpio243 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 107 ebi 256 d_cs0_ gpio256 p d_cs0 ebi chip select 0 o f v dde9 ?/up ?/up ? ? ad9 a1 ?? ? a2 ?? ? g gpio256 gpio i/o 257 d_cs2_d_add_dat31_ gpio257 p d_cs2 ebi chip select 2 o f v dde8 ?/up ?/up ? ? u1 a1 d_add_dat31 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio257 gpio i/o 258 d_cs3_d_tea_ gpio258 p d_cs3 ebi chip select 3 o f v dde8 ?/up ?/up ? ? t6 a1 d_tea ebi transfer error acknowledge i a2 ?? ? g gpio258 gpio i/o 259 d_add12_ gpio259 p d_add12 ebi address bus i/o f v dde8 ?/up ?/up ? ? r1 a1 ?? ? a2 ?? ? g gpio259 gpio i/o 260 d_add13_ gpio260 p d_add13 ebi address bus i/o f v dde8 ?/up ?/up ? ? r2 a1 ?? ? a2 ?? ? g gpio260 gpio i/o 261 d_add14_ gpio261 p d_add14 ebi address bus i/o f v dde8 ?/up ?/up ? ? r3 a1 ?? ? a2 ?? ? g gpio261 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 108 262 d_add15_ gpio262 p d_add15 ebi address bus i/o f v dde8 ?/up ?/up ? ? r4 a1 ?? ? a2 ?? ? g gpio262 gpio i/o 263 d_add16_d_add_dat16_ gpio263 p d_add16 ebi address bus i/o f v dde8 ?/up ?/up ? ? r5 a1 d_add_dat16 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio263 gpio i/o 264 d_add17_d_add_dat17_ gpio264 p d_add17 ebi address bus i/o f v dde8 ?/up ?/up ? ? t5 a1 d_add_dat17 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio264 gpio i/o 265 d_add18_d_add_dat18_ gpio265 p d_add18 ebi address bus i/o f v dde8 ?/up ?/up ? ? t2 a1 d_add_dat18 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio265 gpio i/o 266 d_add19_d_add_dat19_ gpio266 p d_add19 ebi address bus i/o f v dde8 ?/up ?/up ? ? t3 a1 d_add_dat19 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio266 gpio i/o 267 d_add20_d_add_dat20_ gpio267 p d_add20 ebi address bus i/o f v dde8 ?/up ?/up ? ? t4 a1 d_add_dat20 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio267 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 109 268 d_add21_d_add_dat21_ gpio268 p d_add21 ebi address bus i/o f v dde9 ?/up ?/up ? ? ab11 a1 d_add_dat21 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio268 gpio i/o 269 d_add22_d_add_dat22_ gpio269 p d_add22 ebi address bus i/o f v dde9 ?/up ?/up ? ? ad10 a1 d_add_dat22 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio269 gpio i/o 270 d_add23_d_add_dat23_ gpio270 p d_add23 ebi address bus i/o f v dde9 ?/up ?/up ? ? ae10 a1 d_add_dat23 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio270 gpio i/o 271 d_add24_d_add_dat24_ gpio271 p d_add24 ebi address bus i/o f v dde9 ?/up ?/up ? ? af10 a1 d_add_dat24 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio271 gpio i/o 272 d_add25_d_add_dat25_ gpio272 p d_add25 ebi address bus i/o f v dde9 ?/up ?/up ? ? ad11 a1 d_add_dat25 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio272 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 110 273 d_add26_d_add_dat26_ gpio273 p d_add26 ebi address bus i/o f v dde9 ?/up ?/up ? ? ae11 a1 d_add_dat26 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio273 gpio i/o 274 d_add27_d_add_dat27_ gpio274 p d_add27 ebi address bus i/o f v dde9 ?/up ?/up ? ? af11 a1 d_add_dat27 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio274 gpio i/o 275 d_add28_d_add_dat28_ gpio275 p d_add28 ebi address bus i/o f v dde9 ?/up ?/up ? ? ad12 a1 d_add_dat28 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio275 gpio i/o 276 d_add29_d_add_dat29_ gpio276 p d_add29 ebi address bus i/o f v dde9 ?/up ?/up ? ? ab12 a1 d_add_dat29 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio276 gpio i/o 277 d_add30_d_add_dat30_ gpio277 p d_add30 ebi address bus i/o f v dde9 ?/up ?/up ? ? ae12 a1 d_add_dat30 ebi data only in non-mux mode. address and data in mux mode. i/o a2 ?? ? g gpio277 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 111 278 d_add_dat0_ gpio278 p d_add_dat0 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? p25 a1 ?? ? a2 ?? ? g gpio278 gpio i/o 279 d_add_dat1_ gpio279 p d_add_dat1 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? p26 a1 ?? ? a2 ?? ? g gpio279 gpio i/o 280 d_add_dat2_ gpio280 p d_add_dat2 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? n24 a1 ?? ? a2 ?? ? g gpio280 gpio i/o 281 d_add_dat3_ gpio281 p d_add_dat3 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? n25 a1 ?? ? a2 ?? ? g gpio281 gpio i/o 282 d_add_dat4_ gpio282 p d_add_dat4 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? n26 a1 ?? ? a2 ?? ? g gpio282 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 112 283 d_add_dat5_ gpio283 p d_add_dat5 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? m25 a1 ?? ? a2 ?? ? g gpio283 gpio i/o 284 d_add_dat6_ gpio284 p d_add_dat6 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? n22 a1 ?? ? a2 ?? ? g gpio284 gpio i/o 285 d_add_dat7_ gpio285 p d_add_dat7 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? m24 a1 ?? ? a2 ?? ? g gpio285 gpio i/o 286 d_add_dat8_ gpio286 p d_add_dat8 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? m23 a1 ?? ? a2 ?? ? g gpio286 gpio i/o 287 d_add_dat9_ gpio287 p d_add_dat9 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? m22 a1 ?? ? a2 ?? ? g gpio287 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 113 288 d_add_dat10_ gpio288 p d_add_dat10 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? l26 a1 ?? ? a2 ?? ? g gpio288 gpio i/o 289 d_add_dat11_ gpio289 p d_add_dat11 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? l25 a1 ?? ? a2 ?? ? g gpio289 gpio i/o 290 d_add_dat12_ gpio290 p d_add_dat12 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? l24 a1 ?? ? a2 ?? ? g gpio290 gpio i/o 291 d_add_dat13 _gpio291 p d_add_dat13 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? l23 a1 ?? ? a2 ?? ? g gpio291 gpio i/o 292 d_add_dat14_gpio292 p d_add_dat14 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? l22 a1 ?? ? a2 ?? ? g gpio292 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 114 293 d_add_dat15_gpio293 p d_add_dat15 ebi data only in non-mux mode. address and data in mux mode. i/o f v dde10 ?/up ?/up ? ? k26 a1 ?? ? a2 ?? ? g gpio293 gpio i/o 294 d_rd_wr_gpio294 p d_rd_wr ebi read/write o f v dde10 ?/up ?/up ? ? r26 a1 ?? ? a2 ?? ? g gpio294 gpio i/o 295 d_we0_gpio295 p d_we0 ebi write enable o f v dde8 ?/up ?/up ? ? n1 a1 ?? ? a2 ?? ? g gpio295 gpio i/o 296 d_we1_gpio296 p d_we1 ebi write enable o f v dde8 ?/up ?/up ? ? p5 a1 ?? ? a2 ?? ? g gpio296 gpio i/o 297 d_oe_gpio297 p d_oe ebi output enable o f v dde10 ?/up ?/up ? ? p23 a1 ?? ? a2 ?? ? g gpio297 gpio i/o 298 d_ts_gpio298 p d_ts ebi transfer start o f v dde9 ?/up ?/up ? ? ae9 a1 ?? ? a2 ?? ? g gpio298 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 115 299 d_ale_gpio299 p d_ale ebi address latch enable o f v dde10 ?/up ?/up ? ? p24 a1 ?? ? a2 ?? ? g gpio299 gpio i/o 300 d_ta_gpio300 p d_ta ebi transfer acknowledge i/o f v dde9 ?/up ?/up ? ? af9 a1 ?? ? a2 ?? ? g gpio300 gpio i/o 301 d_cs1_gpio301 p d_cs1 ebi chip select o f v dde9 ?/up ?/up ? ? ab10 a1 ?? ? a2 ?? ? g gpio301 gpio i/o 302 d_bdip_gpio302 p d_bdip ebi burst data in progress o f v dde8 ?/up ?/up ? ? m2 a1 ?? ? a2 ?? ? g gpio302 gpio i/o 303 d_we2_gpio303 p d_we2 ebi write enable o f v dde8 ?/up ?/up ? ? n2 a1 ?? ? a2 ?? ? g gpio303 gpio i/o 304 d_we3_gpio304 p d_we3 ebi write enable o f v dde8 ?/up ?/up ? ? n3 a1 ?? ? a2 ?? ? g gpio304 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 116 305 d_add9_gpio305 p d_add9 ebi address bus i/o f v dde8 ?/up ?/up ? ? p1 a1 ?? ? a2 ?? ? g gpio305 gpio i/o 306 d_add10_gpio306 p d_add10 ebi address bus i/o f v dde8 ?/up ?/up ? ? p2 a1 ?? ? a2 ?? ? g gpio306 gpio i/o 307 d_add11_gpio307 p d_add11 ebi address bus i/o f v dde8 ?/up ?/up ? ? p3 a1 ?? ? a2 ?? ? g gpio307 gpio i/o reset and clocks ? reset p reset external reset input i mh v ddeh1 reset/up reset/up m2 r2 n5 230 rstout p rstout external reset output o mh v ddeh1 rstout/low rstout/ high a3 a3 a3 211 bootcfg0_irq2_ gpio211 p bootcfg0 boot configuration i mh v ddeh1 bootcfg/ down bootcfg/ down ??l4 a1 irq2 i a2 ?? ? g gpio211 gpio i/o 212 bootcfg1_irq3_ gpio212 p bootcfg1 boot configuration i mh v ddeh1 bootcfg/ down input/down l1 n2 l3 a1 irq3 external interrupt request i a2 ?? ? g gpio212 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 117 213 wkpcfg_nmi_ gpio213 p wkpcfg weak pull configuration input i mh v ddeh1 wkpcfg/up input/up ? n3 m5 a1 nmi critical interrupt to core 11 i a2 ?? ? g gpio213 gpio i 208 pllcfg0_irq4_ gpio208 p pllcfg0 fmpll mode configuration input i mh v ddeh1 pllcfg/up input/up m3 r3 m3 a1 irq4 external interrupt request i a2 ?? ? g gpio208 gpio i/o 209 pllcfg1_irq5_ gpio209 p pllcfg1 fmpll mode configuration input i mh v ddeh1 pllcfg/up input/up (for rev2 of the device: ?/up) l2 p2 l1 a1 irq5 external interrupt request i a2 soutd dspi d data output o g gpio209 gpio i/o ? pllcfg2 p pllcfg2 fmpll mode configuration input i mh v ddeh1 pllcfg/ down pllcfg/ down l3 p3 l2 ?xtal p xtal crystal oscillator output o ae v dd33 xtal xtal w22 ac26 ac26 ?extal p extal crystal oscillator input i ae v dd33 extal extal v22 ab26 ab26 229 d_clkout p d_clkout ebi system clock output o f v dde9 clkout/ enabled clkout/ enabled ??af12 214 engclk p engclk ebi engineering clock output note: extclk (external clock input) selected through siu register) of v dde2 engclk/ enabled engclk/ enabled aa1 ad1 ad1 jtag and nexus (see footnote 12 about resets) ?evti ? 13 evti nexus event in i f v dde2 ?/up evti/up n4 t4 v1 227 evto (the bam uses this pin to select if auto baud rate is on or off) ? 13 evto nexus event out o f v dde2 abs/up evto/hi p1 u1 v2 219 mcko ? 13 mcko nexus message clock out o f v dde2 o/low disabled 14 n2 t2 u4 table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 118 220 mdo0_gpio220 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo0 15 nexus message data out o f v dde2 o/low mdo0/low p3 u3 v3 a1 ?? ? a2 ?? ? g gpio220 gpio i/o 221 mdo1_gpio221 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo1 15 nexus message data out o f v dde2 o/low ?/down p4 u4 w6 a1 ?? ? a2 ?? ? g gpio221 gpio i/o 222 mdo2_gpio222 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo2 15 nexus message data out o f v dde2 o/low ?/down r1 v1 v4 a1 ?? ? a2 ?? ? g gpio222 gpio i/o 223 mdo3_gpio223 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo3 15 nexus message data out o f v dde2 o/low ?/down r2 v2 v5 a1 ?? ? a2 ?? ? g gpio223 gpio i/o 75 mdo4_gpio75 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo4 15 nexus message data out o f v dde2 o/low ?/down r3 v3 w1 a1 ?? ? a2 ?? ? g gpio75 gpio i/o 76 mdo5_gpio76 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo5 15 nexus message data out o f v dde2 o/low ?/down r4 v4 w2 a1 ?? ? a2 ?? ? g gpio76 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 119 77 mdo6_gpio77 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo6 15 nexus message data out o f v dde2 o/low ?/down t1 w1 w3 a1 ?? ? a2 ?? ? g gpio77 gpio i/o 78 mdo7_gpio78 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo7 15 nexus message data out o f v dde2 o/low ?/down t2 w2 y1 a1 ?? ? a2 ?? ? g gpio78 gpio i/o 79 mdo8_gpio79 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo8 15 nexus message data out o f v dde2 o/low ?/down t3 w3 w5 a1 ?? ? a2 ?? ? g gpio79 gpio i/o 80 mdo9_gpio80 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo9 15 nexus message data out o f v dde2 o/low ?/down u1 y1 y2 a1 ?? ? a2 ?? ? g gpio80 gpio i/o 81 mdo10_gpio81 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo10 15 nexus message data out o f v dde2 o/low ?/down u2 y2 y3 a1 ?? ? a2 ?? ? g gpio81 gpio i/o 82 mdo11_gpio82 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo11 15 nexus message data out o f v dde2 o/low ?/down u3 y3 y4 a1 ?? ? a2 ?? ? g gpio82 gpio i/o table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 120 231 mdo12_gpio231 ? 13 mdo12 15 nexus message data out o f v dde2 o/low ?/down v1 aa1 y5 a1 ?? ? a2 ?? ? g gpio231 gpio i/o 232 mdo13_gpio232 ? 13 mdo13 15 nexus message data out o f v dde2 o/low ?/down w2 aa2 aa1 a1 ?? ? a2 ?? ? g gpio232 gpio i/o 233 mdo14_gpio233 ? 13 mdo14 15 nexus message data out o f v dde2 o/low ?/down v3 aa3 aa2 a1 ?? ? a2 ?? ? g gpio233 gpio i/o 234 mdo15_gpio234 ? 13 mdo15 15 nexus message data out o f v dde2 o/low ?/down u4 y4 aa3 a1 ?? ? a2 ?? ? g gpio234 gpio i/o 224 mseo0 ? 13 mseo0 15 nexus message start/end out o f v dde2 o/low mseo/hi p2 u2 u6 225 mseo1 ? 13 mseo1 15 nexus message start/end out o f v dde2 o/low mseo/hi n3t3u5 226 rdy ? 13 rdy nexus ready output o f v dde2 o/low rdy/hi m4 r4 u3 ?tck ? 13 tck jtag test clock input i f v dde2 tck/down tck/down y1 ab2 ab2 ?tdi ? 13 tdi jtag test data input i f v dde2 tdi/up tdi/up y2 ac2 ac2 228 tdo ? 13 tdo jtag test data output o f v dde2 tdo/up tdo/up w1 ab1 ab1 ?tms ? 13 tms jtag test mode select input i f v dde2 tms/up tms/up w3 ab3 ab3 ?jcomp ? 13 jcomp jtag tap controller enable i f v dde2 jcomp/down jcomp/down m1 r1 u2 ? test ? test test mode select (not for customer use) ifv ddeh1 test/down test/down b4 b4 b4 ? vddsyn ? vddsyn clock synthesizer power input i vdde v ddsyn vddsyn vddsyn y22 ad26 ad26 table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 121 ? vsssyn ? vsssyn clock synthesizer ground input i vsse v ddsyn vsssyn vsssyn u22 aa26 aa26 ?vstby ? vstby sram standby power input i vhv v ddeh1 vstby vstby k4 m4 m4 ? regsel ? regsel selects regulator mode (linear/switch mode) iaev ddreg regsel regsel v20 w23 w23 ?regctl ? regctl regulator controller output to base/gate of power transistor o ae v ddreg regctl regctl t22 y26 y26 ?vssfl ? vssfl tie to v ss i vss v ddreg vssfl vssfl v21 ab25 ab25 ? vddreg ? vddreg source voltage for on-chip regulators and low voltage detect circuits i vddint v ddreg vddreg vddreg u21 aa25 aa25 1 the gpio number is the same as the corresponding pad configurat ion register (siu_pcrn) number in pins that have gpio functional ity. for pins that do not have gpio functionality, this number is the pcr number. 2 the primary signal name is used as the pin label on the bga map for identification purposes. however, the primary signal functi on is not available on all devices and is indicated by a dash in the following table co lumns: signal functions, p/f/g, and i/o type. 3 p/a/g stands for primary/alternate/gpio . this column indicates which function on a pin is primary, alternate 1, alternate 2, ( alternate n ) and gpio. 4 each line in the function column corresponds to a separate signal function on the pin. for all device i/o pins, the primary, al ternate, or gpio signal functions are designated in the pa field of the siu_pcrn registers except wher e explicitly noted. 5 mh = high voltage, medium speed f = fast speed fs = fast speed with slew ae = analog with esd protection circuitry (up/dow n = pull up and pull down circuits included in the pad) vhv = very high voltage 6 vdde (fast i/o) and vddeh (slow i/o) power supply inputs are gro uped into segments. each segment of vddeh pins can connect to a separate 3.3?5.0 v (+5%/?10%) power supply input. each segment of vdde pins c an connect to a separate 1.8?3.3 v (10%) power supply. 7 the status during reset pin is sampled after the internal por is negated. prior to exiting por, the signal has a high impedance . the terminology used in this column is: o ? output, i ? input, up ? weak pull up enabled, down ? weak pulldown enabled, low ? output driven low, high ? output driv en high, abs ? au to baud select (during reset or until jcomp assertion). a dash on the left side of the slash denotes that both the input and output buffers fo r the pin are off. a dash on the right side of the slash denotes t hat there is no weak pull up/down enabled on the pin. the signal name to the left or right of the slash i ndicates the pin is enabled. 8 the function after reset of a gpi function is general purpose input. a dash on the left side of the slash denotes that both the input and output buffers for the pin are off. a dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 9 this signal name includes etpu_c functionality that this devi ce does not have. this is for forward compatibility with devices t hat have an etpu_c. 10 during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pu ll resistors are disabled when the system clock propagates through the device. 11 nmi does not have a pcr pa configuration; it is enabled when nmi is enabled through the siu_ireer and siu_ifeer registers. table 42. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location 324 416 516 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 122 12 nexus reset is different than system reset; mdo 1-11 are enabled when trace (rpm or fpm) is enabled, and mdo 12-15 when fpm tra ce is enabled. mseo and mcko are also dependent on trace (rpm or fpm) being enabled. 13 the nexus pins don?t have a ?primary? function as they are not configured by the siu. the pins are selected by asserting jcomp and configuring the npc. siu values have no effect on the function of these pins once enabled. 14 mcko is disabled from reset; it can be enabled from the tool (controlled by nexus npc_pcr register). 15 do not connect pin directly to a power supply or ground. mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 123 table 44 lists the pin locations of the power and ground signals on the 324 tepbga package. table 43. 324-pin power supply locations vdd a2 b3 c4 d5 k3 v19 w5 w9 w20 y4 y21 aa3 aa22 ab2 vdd33 w21 v4 vdde2 ab4 m9 n1 n10 n9 p10 p9 t4 w6 v2 vddeh1 vddeh4 vddeh6 vddeh7 b1 l4 ab20 w8 n20 t21 c22 h19 l22 vss a1 a22 aa2 aa21 ab1 ab22 b2 b21 c20 c3 d19 d4 j10 j11 j12 j13 j14 j9 k10 k11 k12 k13 k14 k9 l10 l11 l12 l13 l14 l9 m10 m11 m12 m13 m14 n11 n12 n13 n14 p11 p12 p13 p14 w19 w4 y20 y3 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 124 table 44 lists the pin locations of the power and ground signals on the 416 tepbga package. table 44. 416-pin power supply locations vdd a2 b3 c4 d5 n4 ab4 ab23 ac3 ac12 ac24 ad2 ad25 ae1 ae26 vdd33 m1 aa4 aa23 vdde2 n10 p10 p11 r10 r11 t1 t10 t11 t12 u10 u11 u12 w4 ac1 ac5 af2 vddeh1 vddeh3 vddeh4 vddeh5 b1 p4 ac10 af5 ac11 af22 ac21 af25 vddeh6 vddeh7 n23 ac25 d24 e23 m26 vss a1 a26 b2 b25 c3 c24 d4 d23 k10 k11 k12 k13 k14 k15 k16 k17 l10 l11 l12 l13 l14 l15 l16 l17 m10 m11 m12 m13 m14 m15 m16 m17 n11 n12 n13 n14 n15 n16 n17 p12 p13 p14 p15 p16 p17 r12 r13 r14 r15 r16 r17 t13 t14 t15 t16 t17 u13 u14 u15 u16 u17 ac4 ac23 ad3 ad24 ae2 ae25 af1 af26 mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 125 table 45 lists the pin locations of the power and ground signals on the 516 tepbga package. table 45. 516-pin power supply locations vdd a2 b3 c4 d5 e6 n4 ab4 ab23 ac3 ac12 ac24 ad2 ad25 ae1 ae26 vdd33 vdde10 m1 p6 l21 aa4 aa11 aa14 aa23 f16 f17 f19 f21 n21 p21 aa22 vdde2 n10 p10 p11 r10 r11 t1 t10 t11 t12 u10 u11 u12 w4 ac1 ac5 af2 vdde8 vdde9 f6 f8 f10 f11 n6 aa5 aa13 ab6 ab7 ab18 ab19 ab20 ab21 vddeh1 vddeh3 vddeh4 vddeh5 b1 p4 ac10 af5 ac11 af22 ac21 af25 vddeh6 vddeh7 n23 ac25 d24 e23 m26 vss a25 b2 b25 b26 c3 c24 d4 d23 e5 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 e19 e21 e22 f5 f13 f14 k10 k11 k12 k13 k14 k15 k16 k17 l10 l11 l12 l13 l14 l15 l16 l17 m10 m11 m12 m13 m14 m15 m16 m17 n11 n12 n13 n14 n15 n16 n17 p12 p13 p14 p15 p16 p17 r12 r13 r14 r15 r16 r17 t13 t14 t15 t16 t17 u13 u14 u15 u16 u17 aa6 aa21 ab5 ab22 ac4 ac23 ad3 ad24 ae2 ae25 mpc5674f microcontroller data sheet, rev. 9 signal properties and muxing freescale semiconductor 126 revision history mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 127 appendix b revision history table 46 describes the changes made to this document between revisions. table 46. revision history revision (date) description of changes 2 (sept 2008) initial release, nda required. 3 (nov 2009) changes between rev.2 and rev. 3: added 516-pin package figures. signals table: updates throughout entire table. updated section 4.6, ?power up/down sequencing? updated features list. updated flash pfcpr1 settings table. fixed jtag test clock input timing figure so the spec #?s in table matched figure. updated orderable part numbers table. moved signals table to be an appendix. added 324-pin package thermals. updated part numbers in orderable parts table (missing f: mpc5674f). fmpll electrical spec table: spec #1 changed min values of 4 to 8 removed last sentence of footnote 2 added note "upper tolerance of less than 1% is allowed on 40mhz crystal." oscillator electrical spec table: moved predivider op. frequency spec from this table to the fmpll electrical spec table removed footnote #3 (since vdde9 is an external supply and has no relation to the oscillator, pmc, or pll). added maximum solder temperature to absolute max ratings table. pmc operating conditions table: removed jtemp row. changed vddr to vddreg (naming consistency) changed vdd12 to vdd (naming consistency) pmc electrical spec table: added vddreg to this parameter ?trimmed bandgap reference voltage / voltage dependence (v ddreg )? changed vddstep to lvdstep12 (naming consistency) added two conditons to the opening statements of section 4.6, ?power up/down sequencing .? dc electrical specifications table: spec #9 (fast i/o input high voltage) spec #10 (fast i/o input low voltage) spec #24 (operating curr ent 1.2 v supplies; idd) spec #25 (operating current 3.3 v supplies; iddsyn) spec #32 (analog input current, channel off; iinact_a) footnote #12 ("ioh_s = {11.6} ma...") mpc5674f microcontroller data sheet, rev. 9 revision history freescale semiconductor 128 3 (cont.) eqadc conversion sp ecifications table: spec #7, 8: both +/-3, no dependency on frequency spec #15, 16: added "(with calibration)" to both flash program and erase specifications table: added footnote 4 to spec #2. updated all initial max value times. updated entire ac specific ations: clocking section. pad ac specifications tabl e: updated medium pad specs derated pad ac specifications table: updated all specs updated entire section 4.6, ?power up/down sequencing .? updated absolute maximum ratings (amr) specs 1?11, 15, 16. changed name of iddc to iregctl since it is the regctl max drive current. added two emc radiated emissions operating behaviors tables and removed ?emi testing specifications? table. pmc electrical specifications table: 1b: changed 1% to 2% 1c: changed 150 to 300 ppm/c 2b: added footnote 2c: changed from "trimming step vdd" to "trimming step vdd12out" dc electrical specifications table: 6: updated min value and added keep-out range standby ram regulator electrical specifications table: added brownout spec pmc electrical spec table, added new specs: smps regulator output resistance, spms regulator clock frequency, smps regulator overshoot at start-up, smps max output current, and voltage variation on current step. added lvd vdda specs to the pmc electrical spec table. removed specs for vddf and vflash since those supplies are shorted with others in the package. 4 (aug 2010) changes between rev.3 and rev.4: table ?derated pad ac specifications ?, spec #1: changed 20ns to 200ns. added ?324-ball tepbga pin assignments? section and mechanical drawings. appendix a (signals): added ?(the bam uses this pin to select if auto baud rate is on or off)? to the evto pin description. added 324 pinout column. changed footnote from ?nmi does not have a pcr pa conf iguration; it is enabled when nmi is enabled through the siu direr register.? to ?nmi doe s not have a pcr pa configuration; it is enabled when nmi is enabled through the siu_ireer and siu_ifeer registers.? updated eqadc signals to show that eqadc a and b each have dedicated channels (anx0-23) and shared channels (an24-39). table 46. revision history (continued) revision (date) description of changes revision history mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 129 4 (cont) ?temperature sensor electrical specif ications? table: changed spec #2 to have one temperature range (-40 - 150 c) and changed spec value from 1.0 to 10.0 c. ?eqadc conversion specifications (operating)? table: changed spec #13 (non-disruptive injection current) values from 1 to 3. "ipclkdiv settings" table, removed footnote "e mios and dma are not considered peripherals here." 5 (feb-2011) note 4 in maximum ratings updated from 2.0 v to 1.65 v. changed i/o supply voltage spec in dc electrical specs, spec 2, from 1.62 v min to 3.0 v min. changed the apc=rwsc value in line 1 of pfcpr1 setti ngs vs. frequency of operation table from 0b011 to 0b100 changed note 1 for pad ac specifications table from v dde = 1.62 v to 1.98 v to read vdde = 3.0 v to 3.6 v changed note 6 for signal properties and muxing summary table by removing the voltage range 1.8 v - 3.3 v to have 3.3 v instead of the range. spec 2 in table 9 ?esd ratings? the spec for ?esd fo r charged device model (cdm)? changed to 250 v (other) from 500 v (other) removed voltage ranges 1.62-1.98 v and 2.25-2.75 v from spec 28 in table 14 6 (feb-2011) same content as for rev. 5 7 (mar-2011) added entry for rev. 6 and rev. 7 to this table to fix a revision-numbering issue. 8 (jun-2011) added the following footnotes to the ?s ignal properties and muxing summary? table: ? footnote 10, for the ana[0:7] signals, ?during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pull resistors are disabled when the system clock propagates through the device.? ? footnote 15, for mdo[0:15] and mseo[0:1] signals, ?do not connect pin directly to a power supply or ground.? changed min and max values of id 1 ?nominal bandgap reference voltage? in table 11 (pmc electrical specifications) to 0.608 v min and 0.632 v max. changed min and max values of spec 2 ?adc bandgap? in table 23 (adc band gap reference/lvi electrical specifications) to 1.171 v min and 1.269 v max. changed spec 3 of table 26 (flash eeprom module life) from 'minimum data retention at 25 c ambient temperature' to 'minimum data re tention at 85 c ambient temperature' added spec 41, 42, 43 and 44 to the ?dc electrical specifications? table added note 25 to the ?dc electrical specifications? table for spec 41, 42 and 43 added note 26 to the ?dc electr ical specifications? for spec 44 added spec 17 to the ?eqadc conversi on specifications (operating)? table. added spec 18 to the ?eqadc conversi on specifications (operating)? table. added note 15 to the ?eqadc conversion specific ations (operating)? table for spec 17 and 18. table 46. revision history (continued) revision (date) description of changes mpc5674f microcontroller data sheet, rev. 9 revision history freescale semiconductor 130 8 (jun-2011) removed spec 3 from table 27 ?pfcpr1 settings vs frequency of operation? updated spec 2a (untrimmed vrc 1.2v) in table 11 ?p mc electrical specifications? to a max value of vdd12out + 17%. updated item 26 (operating current vdda supply) in tabl e 14 ?electrical specificatio ns? from 30 ma to 40 ma. updated note 11 for table 14 (electrical specif ications) to read ioh_f = {16,32,47,77} ma and iol_f = {24,48,71,115} ma for {00,01,1 0,11} drive mode with vdde = 3.0 v. updated id 9 in table 11 (pmc electrical specifications) to v reg = 4.5 v, max dc output curr ent with a max of 80 ma v reg = 4.25 v, max dc output current, crank condition with a max of 40 ma updated table 17 (dspi lvds pad specification) with the following: ? spec 1 typical value updated from 40 mhz to 50 mhz ? spec 2 added src conditions and associated values: ? src=0b00 or src=0b11 min 150 mv max 400 mv ? src=0b01 min 90 mv max 320 mv ? src=0b10 min 160 mv max 480 mv ? spec 3 - min value from 1.075 v to 1.06 v - max value from 1.325 v to 1.39 v ? added spec 5, 6 and 7 updated table 17 "dspi lvds pad specification" to incl ude temperature with a min va lue of -40 c and max of 150 c updated spec 5 of table 18, "fmpll electrical specifications" to < 400 us as the max vaule. added the sentence "violati ng the vco min/max range ma y prevent the system from ex iting reset." to the end of footnote 16 of table 18, "f mpll electrical specifications" updated spec 1 of table 18, "fmpll electrical specif ications", crystal reference (pllcfg2 = 0b1) minimum value from 40 mhz to 16 mhz. updated spec 1 of table 18, "fmpll el ectrical specifications", external reference (pllcfg2 = 0b1) minimum value from 40 mhz to 16 mhz. removed note 9, 'duty cycle can be 20?80% when pll is used with a pre-divider greater than 1', from table 18, "fmpll electrical specifications". updated id 16 in table 11, ?pmc electrical specificati ons?, smps regulator clock frequ ency (after reset) 2.4mhz max updated table 16 ?flash eeprom module life?, spec 3, ?blocks with 10,001?100,000 p/e cycles? to 5 years. added typ column to table 25, ?flash program and erase specifications? table 46. revision history (continued) revision (date) description of changes revision history mpc5674f microcontroller data sheet, rev. 9 freescale semiconductor 131 updated table 3, ?absolute maximum ratings? with the following: - spec 1, ?1.2 v core supply voltage?, to a max of 2.0 v - spec 3, ?clock synthesizer voltage?, to a max of 5.3 v - spec 4, ?i/o supply voltage? to a max of 5.3 v - spec 5, ?analog supply voltage? to a max of 5.3 v - note 2 to read, ?2.0 v for 10 hours cumula tive time, 1.32 v +10% for time remaining.? - note 3, ?... 5.0 v + 10% ...? to ?... 5.25 v + 10 % ...? - note 5, ?... 3.3 v + 10% ...? to ?... 3.60 v + 10 % ...? updated spec 2 (esd for charged device model (cdm)) of table 9, ?esd ratings?, to 500 v updated table 27, ?pfcpr1 settings vs. frequency of operation?, spec 3, apc = rwsc column to 0b100. updated spec 26, ?operating current 5.0 v supplies @ f sys = 264 mhz? for i dda to 50 ma, in table 14, ?dc electrical specifications?. table 46. revision history (continued) revision (date) description of changes mpc5674f microcontroller data sheet, rev. 9 revision history freescale semiconductor 132 9 (oct-2012) updated table 1 (orderable part numbers) with actual available parts.added new part number spc5673ff3mvy2 ,package description 516 pbga, w/ebi, pb-free.speed is 200mhz nom and max. ?removed note attached to ?orderable part numbers? and ?free scale part number?. updated footnotes of table 3 (absolute maximum ratings) to: ? 2.0 v for 10 hours cumulative ti me, 1.2v +10% for time remaining. ? 6.4 v for 10 hours cumulative ti me, 5.0v +10% for time remaining. ? 5.3 v for 10 hours cumulative ti me, 3.3v +10% for time remaining. updated table 6 (thermal characteristics, 324-pin package) to show mpc5674f thermal characteristics. in table 10 (pmc operating conditions) updated the parameter ?supply voltage vdd 1.2v nominal" to ?core supply voltage". in table 11 (pmc electrical specifications) updated the following rows: ?parameter ?nominal vrc regulated 1.2v ou tput vdd? updated column ?typ? to 1.27 v. ?the minimum and maximum value of ?untrimmed vrc 1.2v output variation before band gap trim (unloaded)? updated to ?-14%? and ?+10%? respectively. ?the minimum and maximum value of ?trimmed vrc 1.2v output variation after band gap trim (regctl load max. 20ma, vdd load max 1a)? updated to ?-10%? and ?+5%? respectively. in table 12 (power sequence pin states for mh and ae pads) updated the row(vdd33 = low, vdde = high), parameter ?mh+lvds pads? to ?outputs disabled?. in table 13 (power sequence pin states for f and fs pads) updated the rows (vdd = low, vdd33 = low, vdde = high) and (vdd = high, vdd33 = low, vdde = high) ,param eter ?f and fs pad? to ?outputs disabled?. in table 14 (dc electrical specifications) updated the spec 24 ?operating current 1.2 v supplies @ f sys = 264 mhz? with 'v dd @ 1.32 v' max value to 850 ma from 1.0 a, and deleted corresponding footnote stating that the previous information was preliminary. updated current(ma) values in table 15 (v dde /v ddeh i/o pad average dc current) from spec 5 to 13. -spec 5 current (ma) from 6.5 to 7.4 -spec 6 current (ma) from 9.4 to 10.5 -spec 7 current (ma) from 10.8 to 12.3 -spec 8 current (ma) from 33.3 to 35.2 -spec 9 current (ma) from 12.0 to 12.7 -spec 10 current (ma) from 6.2 to 6.7 -spec 11 current (ma) from 4.0 to 4.2 -spec 12 current (ma) from 2.4 to 2.6 -spec 13 current (ma) from8.9 to 9.1 updated 'tck low to tdo data valid' spec (t tdov ) in the table 33 (jtag pin ac electrical characteristics) to a max value of 12.5 ns. updated 'tck low to tdo data valid' spec (t ntdov ) in the table 34 (nexus debug port timing) to a max value of 12.5 ns. ?updated the footnote of parameter ?t cyc ? to ?see notes on tcyc in ta b l e 2 7 ?.removed references to ?section i/o pad vdd33 current specifications? . table 46. revision history (continued) revision (date) description of changes document number: mpc5674f rev. 9 10/2012 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. arm is the registered trademark of arm limited. arm7tdmi-s is the trademark of arm limited. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org ? freescale semiconductor, inc. 2008-2012. all rights reserved. |
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